Three logic state input buffers

Details Three logic state input buffers Three logic state input buffers

1977-09-16

1979-08-07

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307251, 307DIG1, H03K 1920, H03K 1908, H03K 1730, H03K 1760

Patent

active

041639073

ABSTRACT:
A buffer having a single input and a pair of outputs providing three unambiguous logic output states including a first output connected directly to the input and a second output connected to the junction of a common gate configured FET and an impedance. The input is also connected to the source and body of the FET and a voltage source is connected to the impedance. The first output varies with the input for a first polarity input signal and the second output varies with the input for the opposite polarity input signal.

REFERENCES:
patent: 3609411 (1971-09-01), Ma et al.
patent: 3845328 (1974-10-01), Hollingsworth
patent: 3851189 (1974-11-01), Moyer
patent: 3944848 (1976-03-01), Heeren
patent: 3969633 (1976-07-01), Paluck et al.
patent: 3991326 (1976-11-01), Kawagoe et al.

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