Three-level MOS logic circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307451, H03K 1920, H03K 19094

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active

045188750

ABSTRACT:
A ternary logic circuit comprises a load element connected to one voltage level and to a node and a logic section connected to a second voltage level and the same node from which the circuit output is derived. The two voltage levels including the voltage supply and ground voltage enable the circuit to provide an output at three logic levels, "0", "1", and "2", depending on inputs to the logic section. The circuit may be implemented with CMOS technology using, in addition, N-channel or P-channel depletion devices, in different logic formats such as ternary extensions of NAND or NOR gate circuits with the logic section elements arranged in different configurations and combinations of pairs of CMOS devices.

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Dansky, "Multiple Threshold IGFET Ternary Circuits", IBM Tech. Disc. Bull., vol. 17, No. 5, Oct. 1974, pp. 1356-1357.
Smith, "The Prospects for Multivalued Logic: A Technology and Applications View", IEEE Transactions on Computers, vol. C-30, No. 9, Sep. 1981, pp. 619-634.

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