Three level memory hierarchy using write and share flags

Details Three level memory hierarchy using write and share flags Three level memory hierarchy using write and share flags

1981-12-31

1984-04-10

Smith, Jerry

Boots, shoes, and leggings

G06F 1300

Patent

active

044424876

ABSTRACT:
A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory levels one and two how a given page of information is to be used. Essentially, pages which can be both written and shared are moved from main memory to the shared level two cache and then to the shared level one cache, with the processors executing from the shared level one cache. All other pages are moved from main memory to the private level two and level one caches of the requesting processor. Thus, a processor executes either from its private or shared level one cache. This allows several processors to share a level three common main memory without encountering cross interrogation overhead.

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IBM Technical Disclosure Bulletin, vol. 21, No. 6 Nov. 1978, pp. 2468-2469 F. J. Sparacio "Data Processing System with Second Level Cache".

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