Three level interconnect process for manufacture of integrated c

Details Three level interconnect process for manufacture of integrated c Three level interconnect process for manufacture of integrated c

1979-10-11

1981-07-28

Rutledge, L. Dewayne

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 148 15, 148174, 148187, 148188, 357 23, 357 41, 357 51, 357 59, 357 91, H01L 21265, H01L 21225

Patent

active

042802717

ABSTRACT:
An improved MOS device and method of making it are provided which utilize basically the standard N-chanel self-aligned silicon gate structure and process with implants for self-alignment, modified to allow three levels of interconnects. A P-type substrate is used as the starting material, with N+ source and drain regions defined prior to a polycrystalline silicon gate; thus the source and drain may run under polysilicon. Self-aligning implants after the polysilicon is defined produce the advantages of self-aligned gates.

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patent: 4055444 (1977-10-01), Rao
patent: 4061506 (1977-12-01), McElroy
patent: 4069067 (1978-01-01), Ichinobe
patent: 4084311 (1978-04-01), Yasuoka et al.

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