Three layer floating gate memory transistor with erase gate over

Details Three layer floating gate memory transistor with erase gate over Three layer floating gate memory transistor with erase gate over

1980-03-17

1982-05-25

Clawson, Jr., Joseph E.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 54, 357 59, 365185, H01L 2978

Patent

active

043319688

ABSTRACT:
A field effect transistor storage device for use in programmable read-only memories of the type employing a floating gate and a control gate overlying and aligned with the floating gate. An erase gate is provided adjacent at least one edge of the floating gate for removing charge stored on the floating gate. A method of electrically erasing the storage device includes holding the control gate at a fixed potential to thereby hold the floating gate at a substantially fixed potential while a relatively low voltage is applied to the erase gate to remove charge stored on the floating gate.

REFERENCES:
patent: 3755721 (1973-08-01), Frohman-Bentchkowsky
patent: 3996657 (1976-12-01), Simko et al.
patent: 4099196 (1978-07-01), Simko
patent: 4115914 (1978-09-01), Harari
patent: 4142920 (1979-03-01), Morgan
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
A. Scheibe et al., "Tech. of a New N-Channel One-Transistor Earom Cell Called Simos," IEEE Trans. on Elec. Dev., vol. Ed.-24, #5, May 1977, pp. 600-606.
C. Neugebauer et al., "Electrically Eras. Buried-Gate Nonvol. Read-Only Mem.," IEEE Trans. on Elec. Dev., vol. Ed-24, #5, May 1977, pp. 613-618.

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