Three input variable subfield comparation for fast matching

Details Three input variable subfield comparation for fast matching Three input variable subfield comparation for fast matching

2005-03-08

2005-03-08

Ngo, Chuong (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S709000

Reexamination Certificate

active

06865590

ABSTRACT:
The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.

REFERENCES:
patent: 5144577 (1992-09-01), Linnenberg
patent: 5923579 (1999-07-01), Widigen et al.
patent: 6292818 (2001-09-01), Winters
patent: 6466960 (2002-10-01), Winters

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