Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-05-12
2002-09-10
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S709000
Reexamination Certificate
active
06449629
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to adders and more particularly to adders in which a split-add operation can be utilized to increase computational throughput.
BACKGROUND OF THE INVENTION
Addition forms the basis of many processing operations including counting, subtraction, multiplication and filtering. A wide variety of adder circuits that add binary numbers provide an implementation with a trade-off between the speed of completing the addition operation and the amount of hardware, as measured by area required on an integrated circuit, to complete an addition operation. While three binary number representations are available, sign-magnitude, one's complement, and two's complement, computations are more efficient using the two's complement number representation. Adders can be used to accomplish subtraction by generating the two's complement of the subtrahend and adding the minuend. The two's complement of the subtrahend can be generated internal to the adder by providing the subtrahend in one's complement representation and adding one using the carry-in input to the adder.
A split adder is an adder that is capable of operating in a non-split mode on operands having a relatively large number of bits, and in split mode is capable of operating as more than one adder on operands having relatively fewer bits. Split adders are employed to take advantage of existing hardware where a tradeoff between precision and the number of adders can be made, and to gain additional computational throughput without requiring additional hardware. Split-adders in which the most significant bit portion of two operands are added in a first portion of an adder, and the least significant bit portions of two operands are added in a second portion of an adder are known. Known split-adders, however, can not accommodate more than two operands as inputs.
SUMMARY OF THE INVENTION
In accordance with the invention, an integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circuit receives another portion of the operands to be summed, along with the corresponding carry-in inputs. Multiplexers between the first and second adder circuits determine whether the carry-in inputs to the second adder circuit are the same as the carry-in inputs to the first adder circuit or whether the carry-in inputs to the second adder circuit are independent.
REFERENCES:
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4768160 (1988-08-01), Yokoyama
patent: 5189636 (1993-02-01), Patti et al.
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5390135 (1995-02-01), Lee et al.
patent: 5493524 (1996-02-01), Guttag et al.
patent: 5757685 (1998-05-01), Ohuchi
patent: 5883824 (1999-03-01), Lee et al.
patent: 5933362 (1999-08-01), Inoue
patent: 6003125 (1999-12-01), Shippy
Agere Systems Guardian Corp.
Mai Tan V.
Smith David L.
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