Three-input multiplier and multiplier core circuit used therefor

Details Three-input multiplier and multiplier core circuit used therefor Three-input multiplier and multiplier core circuit used therefor

1997-08-29

2000-02-29

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

327119, G06F 744

Patent

active

060314095

ABSTRACT:
A three-input multiplier core circuit for multiplying first, second, and third initial input voltages V.sub.x, V.sub.y, and V.sub.z is provided, which is operable at a low supply voltage such as approximately 1 V is provided. This circuit includes an octtail cell having first to eighth bipolar transistors whose emitters are coupled together to be connected to a common constant current source/sink. Collectors of the first to fourth transistors are coupled together to form one of a pair of output terminals, and collectors of the fifth to eighth transistors are coupled together to form the other of the pair thereof. An output including the multiplication result is differentially derived from the pair of output terminals. Bases of the first to eighth transistors are respectively applied with voltages V.sub.1 to V.sub.8, where V.sub.1 =aV.sub.x +bV.sub.y +cV.sub.z, V.sub.2 =aV.sub.x +(b-1)V.sub.y +(c-1)V.sub.z, V.sub.3 =(a-1)V.sub.x +bV.sub.y +(c-1)V.sub.z, V.sub.4 =(a-1)V.sub.x +(b-1)V.sub.y +cV.sub.z, V.sub.5 =(a-1)V.sub.x +(b-1)V.sub.y +(c-1)V.sub.z, V.sub.6 =(a-1)V.sub.x +bV.sub.y +cV.sub.z, V.sub.7 =aV.sub.x +(b-1)V.sub.y +cV.sub.z, and V.sub.8 =aV.sub.x +bV.sub.y +(c-1)V.sub.z, where a, b, and c are constants.

REFERENCES:
patent: 5438296 (1995-08-01), Kimura
patent: 5444648 (1995-08-01), Kimura
patent: 5581210 (1996-12-01), Kimura
patent: 5617052 (1997-04-01), Kimura
patent: 5640121 (1997-06-01), Kimura
J. Choma, Jr., "A Three-Level Broad-Banded Monolithic Analog Multiplier," IEEE Journal of Solid-State Circuits, vol. SC-16, No. 4, Aug. 1981, pp. 329-399.

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