Three-gate hazard-free polarity hold latch

Details Three-gate hazard-free polarity hold latch Three-gate hazard-free polarity hold latch

1982-04-26

1984-03-27

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307247R, 307480, 307289, H03K 3037, H03K 1920, H03K 1704

Patent

active

044396902

ABSTRACT:
A hazard-free latch is disclosed comprising three NAND logic gates, one of the gates, in combination with its output loading, being relatively fast and another of the gates, in combination with its output loading, being relatively slow. Both gates receive an input clock signal. Input data is applied to the third gate. The output of the fast gate is connected to another input of the slow gate. The outputs of the third and the slow gates are connected to an output terminal and to another input of the fast gate.

REFERENCES:
patent: 3603815 (1971-09-01), Rao
patent: 3740590 (1973-06-01), Hart et al.
patent: 4160173 (1979-07-01), Aoki
patent: 4283640 (1981-08-01), Konian et al.
patent: 4374331 (1983-02-01), Yamamoto et al.
Gates et al., "Set/Reset Shift Register Latch", IBM Tech. Discl. Bull., vol. 21, No. 10, pp. 4166, Mar. 1979.

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