Patent
1978-11-29
1981-06-23
Wojciechowicz, Edward J.
357 45, 357 55, 357 60, 357 71, 357 76, 357 90, H01L 2348
Patent
active
042754100
ABSTRACT:
A large scale parallel architecture in which many parallel channels numbering 10.sup.2 or more operate simultaneously to create a natural and efficient organization for processing two-dimensional arrays of data. The architecture comprises a plurality of stack integrated circuit wafers having top and bottom surfaces, electric signal paths extending through each of the wafers between the surfaces, and micro-interconnects (smaller than 50 mil) on the surfaces of adjacent wafers interconnecting the respective eletric signal paths with a topographical one-to-one correspondence.
REFERENCES:
patent: 3648131 (1972-03-01), Stuby
patent: 3982268 (1976-09-01), Anthony et al.
IBM Tech. Disc. Bull.-vol. 17, No. 3, Aug. 1974, Noth, p. 656.
Chow Kuen
Grinberg Jan
Jacobson Alexander D.
Hughes Aircraft Company
MacAllister W. H.
Sternfels Lewis B.
Wojciechowicz Edward J.
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