Three-dimensionally stacked nonvolatile semiconductor memory

Details Three-dimensionally stacked nonvolatile semiconductor memory Three-dimensionally stacked nonvolatile semiconductor memory

2011-07-19

2011-07-19

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S165000

Reexamination Certificate

active

07983084

ABSTRACT:
A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

REFERENCES:
patent: 7679133 (2010-03-01), Son et al.
patent: 7821058 (2010-10-01), Kidoh et al.
patent: 7852676 (2010-12-01), Maejima
patent: 2007/0252201 (2007-11-01), Kito et al.
patent: 2007-266143 (2007-10-01), None
U.S. Appl. No. 12/394,487, filed Feb. 27, 2009, Naoya Tokiwa et al.

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