Three-dimensional warp-resistant integrated circuit module metho

Details Three-dimensional warp-resistant integrated circuit module metho Three-dimensional warp-resistant integrated circuit module metho

1995-08-11

1998-09-01

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257686, 257723, 257724, H01L 2160, H01L 2302

Patent

active

058014373

ABSTRACT:
A method and apparatus for achieving a three-dimensional high density warp-resistant integrated circuit module is provided. Selected individual integrated circuit packages which comprise the module are mounted with a thin stiffener, or a thin layer of material having a coefficient of thermal expansion (CTE) less than or equal to that of silicon, and/or are lapped to reduce the package profile, and/or are mounted with a thin layer of material having a CTE greater than that of silicon, and preferably approximately equal to that of the casing material.

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Information allegedly written by Emory Garth regarding "Memory Stacks," Applicant received a facsimile from Emory Garth on Jan. 26, 1993, Applicant does not know when this information was written of its validity.
Catalog of Dense-Pac Microsystems, Inc. describing two products: DPS512X16A3 Ceramic 512K X 16 CMOS SRAM Module and DPS512X16AA3 High Speed Ceramic 512K X 16 CMOS SRAM Module, pp. 865-870.

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