Three-dimensional vector co-processor having I, J, and K registe

Details Three-dimensional vector co-processor having I, J, and K registe Three-dimensional vector co-processor having I, J, and K registe

1990-07-16

1993-02-16

Lee, Thomas C.

Boots, shoes, and leggings

395200, 3649208, 3649262, 36493151, 3649377, 364942, 364DIG2, 364736, G06F 15347

Patent

active

051877961

ABSTRACT:
The present invention is a three-dimensional vector co-processing system (3DVCP) including the datapath of a three-dimensional vector co-processor having a register-to-register architecture and being coupled to a general-purpose processor. The source multiplexer and the destination multiplexer of the co-processor uses full cross-bar switches. As such, the three-dimensional co-processor evaluates three-dimensional vectors and scalars while the general-purpose processor performs the other "general purpose" functions. The 3DVCP includes a co-processor interface for synchronizing the three-dimensional vector co-processor and the general-purpose processor. With this interface, the general-purpose processor controls the address bus and control lines of the data bus. The three-dimensional vector co-processor also has an instruction set that enables the control unit to pipeline the program instructions in stages in addition to instruction fetch, fetch instruction, instruction execute, and store-result. The 3DVCP specifically targets vectors of length 3, and expoits the intrinsic parallelism by providing three parallel execution units that can simultaneously operate on all three vector components. Scalar processing does not suffer with this parallel execution approach, whereas it does with a pipelined approach. The execution units are used individually for scalar operations.

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