Three dimensional stacked nonvolatile semiconductor memory

Details Three dimensional stacked nonvolatile semiconductor memory Three dimensional stacked nonvolatile semiconductor memory

2009-03-18

2010-12-14

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185230, C365S185050

Reexamination Certificate

active

07852675

ABSTRACT:
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

REFERENCES:
patent: 5896317 (1999-04-01), Ishii et al.
patent: 6141250 (2000-10-01), Kashimura
H. Tanaka, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15.

Affiliated with

Also associated with

Rating

Three dimensional stacked nonvolatile semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Three dimensional stacked nonvolatile semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three dimensional stacked nonvolatile semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4180258