Three dimensional stacked nonvolatile semiconductor memory

Details Three dimensional stacked nonvolatile semiconductor memory Three dimensional stacked nonvolatile semiconductor memory

2009-03-19

2010-12-14

Auduong, Gene N (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185230, C365S185250

Reexamination Certificate

active

07852676

ABSTRACT:
In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit.

REFERENCES:
patent: 7091890 (2006-08-01), Sasaki et al.
patent: 2009/0010071 (2009-01-01), Lee
patent: 2009/0268522 (2009-10-01), Maejima
patent: 2009/0268523 (2009-10-01), Maejima
patent: 2010/0097858 (2010-04-01), Tokiwa et al.
patent: 2010/0133627 (2010-06-01), Mizukami et al.
H. Tanaka, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 14-15.

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