Three-dimensional stacked LSI

Details Three-dimensional stacked LSI Three-dimensional stacked LSI

1989-12-19

1993-03-02

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

257763, 257765, H01L 2506, H01L 2352, H01L 2354

Patent

active

051914050

ABSTRACT:
Disclosed is a three-dimensionally stacked LSI having a plurality of integrated-circuit layers stacked together, each of which is equipped with a plurality of circuit elements. Each of the circuit elements are equipped a power terminal of its own, which is connected through interlayer via-hole wiring to the power wiring of the uppermost integrated-circuit layer. The power wiring of the uppermost integrated-circuit layer is formed of a metal exhibiting a low electrical resistance, for example, Al, whereas the metal wirings of the other layers, which are exposed to high temperatures when forming the upper layers, are formed of W.

REFERENCES:
patent: 3508209 (1970-04-01), Agusta et al.
patent: 4021838 (1977-05-01), Warwick
patent: 4074342 (1978-02-01), Honn et al.
patent: 4612083 (1986-09-01), Yasumoto et al.
patent: 4902637 (1990-02-01), Kondou et al.
patent: 4939568 (1990-07-01), Kato et al.
Tsao et al., American Institute of Physics, "Tungsten Deposition on Porous Silicon for Formation of Buried Conductors in Single Crystal Silicon", Applied Physics Letters, vol. 49, No. 7, pp. 403-405, Aug. 18, 1986, New York, NY.

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