Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-10-22
2004-03-16
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S778000
Reexamination Certificate
active
06707157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to a three dimensional semiconductor integrated circuit device on which semiconductor chips having a multi-layer interconnection structure are stacked up multiply, and a method for making the same.
2. Description of the Related Art
Various efforts for improving an integration density of a semiconductor integrated circuit device have been attempted for a long period of time. A three dimensional semiconductor integrated circuit device is considered an ultimate semiconductor integrated circuit device. Various proposals have been presented to realize the three dimensional semiconductor integrated circuit device.
FIG. 1
is a view showing a rough structure of a conventional three dimensional semiconductor integrated circuit device.
Referring to
FIG. 1
, a semiconductor integrated circuit device
1
includes a support substrate
10
, and semiconductor chips
11
A to
11
D. A wire pattern
10
A is formed on an upper surface side of the support substrate
10
. A solder bump
10
B is formed on a bottom surface side of the support substrate
10
. The support substrate
10
has a number of semiconductor chips
11
A to
11
D stacked thereon. Respective semiconductor chips
11
A to
11
D include piercing electrodes
11
a
to
11
d
which pierce from upper surfaces to bottom surfaces of the respective semiconductor chips
11
A to
11
D. A two dimensional semiconductor integrated circuit is shouldered on the upper surfaces of the respective semiconductor chips
11
A to
11
D. In a state where the semiconductor chips
11
A to
11
D are piled up on the support board
10
, a piercing electrode exposed from a bottom surface of a semiconductor chip comes in contact with an electrode pad formed on an upper surface of a lower semiconductor chip. Because of this, a three dimensional semiconductor integrated circuit device carrying out a designated function can be obtained. In the three dimensional semiconductor integrated circuit device, it is possible to form a complex circuit by connecting the piercing electrodes with a multi-layer interconnection structure.
FIGS. 2
to
9
are views respectively showing a forming process of a semiconductor chip
11
A as an example of the above-described semiconductor chip.
Referring to
FIG. 2
, an active element, including a gate electrode
22
and diffusion areas
21
A and
21
B, is formed on a silicon substrate
21
. The active element is covered with an inter layer dielectric
23
. Contact holes for exposing the diffusion areas
21
A and
21
B are formed respectively in the inter layer dielectric
23
. Conductive plugs
23
A and
23
B such as a W plug are respectively formed in the contact holes.
In a state shown in
FIG. 2
, a resist film
24
having a resist opening part
24
A is formed on the inter layer dielectric
23
. The inter layer dielectric
23
is done patterning by using the resist film
24
as a mask. An opening part
23
C, corresponding to the piercing electrode
11
a,
is formed in the inter layer dielectric
23
.
Following the process shown in
FIG. 2
, in a process shown in
FIG. 3
, the silicon substrate
21
is done dry-etching through the opening part
23
C. A concave part
21
C corresponding to the piercing electrode
11
a
is formed in the silicon substrate
21
as an extending part of the opening part
23
C.
Following the process shown in
FIG. 3
, in a process shown in
FIG. 4
, a silicon nitride film
25
is formed by a chemical vapor deposition (CVD) method. The silicon nitride film
25
is piled up as covering the upper surface of the inter layer dielectric
23
, an inside wall surface of the opening part
23
C, and an inside wall surface including a bottom surface of the concave part
21
C are covered continuously.
Following the process shown in
FIG. 4
, in a process shown in
FIG. 5
, a copper layer
26
is formed as follows. A titanium nitride film and a copper film are formed on the CVD-silicon nitride film
25
by the CVD method. Furthermore, electrolytic plating for a copper is carried out by using the CVD-copper film as a electrode, so that the copper layer
26
is formed on the silicon nitride film
25
. The copper layer
26
is filled in the concave part
21
C, so that it forms the plug
26
C.
Following the process shown in
FIG. 5
, in a process shown in
FIG. 6
, the copper layer
26
on the inter layer dielectric
23
is removed by a chemical mechanical polishing (CMP) method.
After the process shown in
FIG. 6
, in a process shown in
FIG. 7
, a following inter layer dielectric
27
is formed on the inter layer dielectric
23
. A copper wire pattern
27
A is formed in the inter layer dielectric
27
by a damascene method.
Following the process shown in
FIG. 7
, in a process shown in
FIG. 8
, a following inter layer dielectric
28
is formed on the inter layer dielectric
27
. A copper wire pattern
28
A including a contact plug is formed in the inter layer dielectric
28
by a dual damascene method.
Following the process shown in
FIG. 7
, in a process shown in
FIG. 8
, as a last process, the bottom surface of the silicon substrate
21
is polished, so that the copper plug
26
is exposed. On the exposed copper plug
26
, a diffusion prevention film
29
A is formed on the copper plug
26
C, so that a conductive pad
29
B is formed. With the above-mentioned processes, the semiconductor chip
11
A shown in
FIG. 1
is obtained. In a structure shown in
FIG. 9
, the copper plug
26
C corresponds to the piercing electrode
11
a
shown in FIG.
1
.
According to processes of manufacturing the semiconductor chip
11
A shown in
FIGS. 2-9
, in the process shown in
FIG. 2
in which the concave part
21
C is formed, a diameter of the concave part
21
C is increased more than a diameter of the opening part
23
C. Therefore, an overhang may be formed on an upper end part of the concave part
21
C by the inter layer dielectric
23
. The concave part
21
C is 60 &mgr;m deep while the diameter of the opening part
23
C generally has the diameter of 10 &mgr;m.
In a state where the overhang is formed on the upper end part of the concave part
21
C in the process shown in
FIG. 4
, if the CVD-silicon nitride film is formed as covering the inside wall surface of the concave part
21
C, forming the silicon nitride film on the upper end part of the concave part
21
C which has a narrowed diameter, namely on the opening part
23
C, has a tendency to be promoted. Therefore, an effective diameter of the opening part
23
C becomes narrower. Hence, if the copper layer
26
is tried to be formed by the electrolytic plating in the process shown in
FIG. 4
, it becomes not-enough to grow the copper layer
26
inside of the concave part
21
C. Thus, a problem in that a defect such as a cave
26
c
shown in
FIG. 5
easily occurs inside of the copper plug
26
C. The copper plug
26
C plays an important role for comprising the piercing electrode
11
a.
Hence, if the defect occurs in the piercing electrode
11
a,
a reliability regarding the three dimensional semiconductor integrated circuit device shown in
FIG. 1
will be reduced.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention is to provide a method of manufacturing a novel and useful semiconductor device in which one or more of the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device including a piercing electrode in a semiconductor chip, acting at a high rate, and having high reliance, which can easily form a three dimensional semiconductor integrated circuit device by piling films. The object is also to provide a method of manufacturing the semiconductor device and a semiconductor integrated circuit device comprised of the semiconductor device.
The above objects of the present invention are achieved by a semiconductor device, including a semiconductor substrate having a first surface and a second surface opposite the first surfac
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