Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Power system
Reexamination Certificate
1999-05-10
2001-02-27
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Power system
C702S060000, C716S030000, C707S793000
Reexamination Certificate
active
06195630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to the field of power modeling for logic cells used in EDA applications.
2. Prior Art
In the field of EDA, in one level of abstraction in the design process, integrated circuit (IC) designs are represented by cells (e.g., logic cells) and interconnections between the cells. Often the IC design has associated with it a number of constraints that the EDA system needs to satisfy during logic synthesis and/or optimization. These constraints include timing constraints, area constraints, and power consumption constraints. There are well known EDA processes that determine if a synthesized IC design meets the given constraints and that perform certain steps if the constraints are not met. If a design does not meet one or more constraints after optimization, it is often redesigned by a designer in order to fall within the prescribed constraints. Therefore, it is important for an EDA system to accurately determine the amount of power consumed by the individual cells of the IC design so that the EDA system can accurately report whether or not the IC design, as an aggregation of individual cells, meets the prescribed power constraints.
Circuits or logic elements are represented in EDA by logic cells whose electrical, timing, logic, and power characteristics and behavior are represented in an entry in a library as a library cell. The libraries are stored in a computer readable format within a computer readable memory for use by appropriate EDA processes. The libraries are typically technology dependent, e.g., CMOS, FPGA, etc., and vary by technology manufacturer (e.g., LSI, Xilinx, etc.). The developer of the library of logic cells needs to characterize each individual logic cell and report, in the library, the above logic cell characteristics, including the power consumed by the logic cell. The more accurate are the individual logic cell characterizations found in the logic cell library, the more accurate is the EDA aggregate report regarding all the cells of a given integrated circuit design.
Currently, prior art library developers can only specify one internal power lookup table at each output pin or input pin of a library cell and one leakage power value per library cell. The internal power table associated with an output pin is then referenced when the output pin switches (transitions), regardless of the state of any signals at the time of transition or regardless of which input pin path caused the output transition. An example is shown with reference to
FIG. 1A. A
logic cell
10
is shown having four gates
11
,
13
,
15
,
17
, and
19
and seven inputs, A-G, and one output, O, taken from gate
19
. The prior art library representation for cell
10
includes a power consumption model that indicates a certain amount of estimated power consumption for a transition at the output pin
19
a
, regardless of what signal state or input pin caused the transition. The power consumed by the cell within this prior art power consumption model for a particular output transition is basically an average of all power consumed by the cell as a result of each possible input state that could cause output O to transition.
This prior art modeling technique leads to inaccuracies during power estimation because the actual power consumed by logic cell
10
varies depending on which input caused the output transition or the state (condition) of any signals existing at the time of the transition. For instance, if input G (
FIG. 1A
) caused the output transition, only gate
19
is used to cause output O to transition. However, if inputs A and B caused the output transition, gates
11
,
13
and
19
are used, thereby creating a longer path from the inputs (A/B) to the output (O) and thereby consuming more power over the former case. Although the prior art library model gives an average power consumption estimation by averaging the output transition power consumption over each input transition, for any particular use of logic cell
10
(e.g., for any particular application of logic signals to the inputs A-G) the prior art model can and does often give inaccurate power consumption results. What is needed is a power modeling system and method that advantageously allows power modeling of a library cell to include information regarding the logic cell's power consumption given an input transition over a particular input pin of the logic cell. One aspect of the present invention provides such advantageous functionality.
Furthermore, the prior art power consumption model gives a library cell's power consumption for an output transition regardless of the state of the input signals that caused the transition. In many instances, a logic cell consumes different amounts of power depending on the condition of the input signals that caused the transition. For instance,
FIG. 1B
illustrates a random access memory cell
21
(RAM) having an address bus input (ADDR), a data bus input/output (DATA), a read signal, a write signal, and an enable signal (EN). Depending on whether the RAM cell
21
is in read or write mode (as indicated by the state of input signals), the internal and leakage power used by the RAM cell
21
can be quite different. Also, depending on whether or not RAM cell
21
is enabled also impacts the power consumption of RAM cell
21
. The prior art power model assigns one “averaged” power consumption amount for RAM cell
21
regardless of the state of the input signals. Therefore, the prior art model either reports too much power consumption or too little power consumption for an application of the RAM cell
21
that performs mostly reads or that performs mostly writes (or vice-versa). What is needed is a power modeling system and method that advantageously allows a library cell to include information regarding the logic cell's particular power consumption given a particular condition (e.g., signal state) that exists contemporaneously with a transition causing the power consumption. One aspect of the present invention provides such advantageous functionality.
Another aspect of EDA power estimation is common power. Common power is the power consumed in the common logic among multiple outputs. It is also the power consumed in the logic which may transition without the output changing.
FIG. 1C
illustrates a logic cell
50
for a case of common logic shared between two outputs Y and Z. In this case, input A can cause both outputs Y and Z to change. However, the library developer needs to ensure that the power of gate
51
is not counted twice in the power model. This is difficult to perform in prior art library power modeling because the power consumed for a transition of output Y and Z is reported irrespective of the input lines or the conditions of the input signals that caused the transition. What is also needed is a system to provide accurate power modeling for the common logic case shown in FIG.
1
C.
Internal power is any power dissipated within the boundary of a cell. This includes short circuit power, as well as the power dissipated due to the charging and discharging of any other existing capacitances internal to the cell. This definition does not distinguish between a cell's short circuit power and other power dissipated internally due to the charging and discharging of internal capacitances during switching. Short circuit power is the power consumed by the cell during a signal transition when both the P and N type transistors can be ON simultaneously. During this short time, current flows from Vdd to ground causing short circuit power dissipation. A cell's internal power is the sum of the internal power of all of the cell's inputs and outputs as modeled in the library.
Internal power of a cell is determined by prior art libraries based on: (1) a single value representing the output load capacitance of an output pin of the cell; and (2) a value representing the input transition time of a
Lin Yueqin
Mauskar Ashutosh S.
Nedelchev Ivailo
Olson Janet
Sproch James
Phan Thai
Synopsys Inc.
Teska Kevin J.
Wagner , Murabito & Hao LLP
LandOfFree
Three-dimensional power modeling table having dual output... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Three-dimensional power modeling table having dual output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three-dimensional power modeling table having dual output... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2571240