Three dimensional polymer memory cell systems

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

Reexamination Certificate

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Details

C257S040000, C257S642000, C257SE29170, C257SE51023, C257SE21024, C257SE27104

Reexamination Certificate

active

10899344

ABSTRACT:
Systems and methodologies are provided for forming three dimensional memory structures that are fabricated from blocks of individual polymer memory cells stacked on top of each other. Such a polymer memory structure can be formed on top of control component circuitries employed for programming a plurality of memory cells that form the stacked three dimensional structure. Such an arrangement provides for an efficient placement of polymer memory cell on a wafer surface, and increases amount of die space available for circuit design.

REFERENCES:
patent: 6798068 (2004-09-01), Oglesby
patent: 6885573 (2005-04-01), Sharma et al.
patent: 2006/0002168 (2006-01-01), Krieger et al.

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