Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Patent
1986-10-09
1990-01-16
Macon, Robert S.
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
357 75, 361415, H01L 2328
Patent
active
048947067
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a three-dimensional packaging structure of semiconductor device chips in which a plurality of semiconductor device chips such as IC chips and LSI chips are stacked in their thickness direction to be packaged in a three-dimensional manner in such a way that the respective chips are interconnected. The invention also relates to an elementary unit of the structure and a method for manufacturing the structure.
BACKGROUND ART
In general, this type of semiconductor device chip is flatly packaged in a package, and accordingly such package is very bulky in comparison with the chip itself. As semiconductor devices become more highly integrated and more functional, it becomes more important that such chips be packaged three-dimensionally in a high density condition. In order to stack and three-dimensionally package semiconductor device chips, the following various methods have been proposed.
As a first example of such proposals, there is a method (Japanese Patent Application Laid-Open No. 72,156/1984) that packages carrying IC chips and provided with lead terminals and sockets are stacked to establish alternate connections of the lead terminals and the sockets between the adjacent packages thus stacked This method is advantageous in that the IC chips are easily exchangeable In spite of this advantage, the method suffers from other disadvantages such as: its manufacturing step efficiency is poor since IC chips are packaged one by one; there is no possibility of freely reducing the stacking intervals of the chips, because the sockets restrict such reduction of the stacking intervals; and packaging of a large number of the chips is difficult, because the thickness of an elementary unit of the thus stacked structure can not be reduced thereby restricting the number of pieces of the chips that can be stacked.
As a second example of the proposals, there is a method (IBM Technical Disclosure Bulletin, Vol. 17, No. 10, March 1975, pp 3084-3086, K. R. Grebe) that a film carrier carrying semiconductor device chips is repeatedly folded into an S-shaped construction to stack the chips. While this method is advantageous in easy packaging, this method has a disadvantage that a long wiring length is required to interconnect the chips, so that device-speed is reduced Further, this method has a problem in device-strength, because the chip must be supported only through its portion connected to the film carrier.
As a third example of the proposals, there is a method (Japanese Patent Application No. 140,658/1984) that a bare chip is engaged in a case having a groove the shape of which is similar to that of the chip so as to form an assembly which is received by a plate to establish wiring connections. This method, while advantageous in short wiring length between the chip and the plate, suffers from a poor yield due to difficulty in insulating the chip's end portions and fine working is required in manufacturing a frame having a shape similar to the chip's shape, so that the cost of the thus obtained three-dimensional structure is expensive.
Furthermore, in such a three-dimensional packaging structure, as the number of stacked layers increases, it becomes a serious problem how to dissipate heat generated in the semiconductor device chips. Consequently, it is required that a suitable radiator construction is provided in the three-dimensional packaging structure.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a three-dimensional packaging structure of semiconductor device chips, an elementary unit thereof and a manufacturing method thereof, which solve the above-mentioned problems inherent to the prior art and increase the efficiency of the manufacturing steps thereof by collectively connecting leads (electrode connecting wires) of the semiconductor device chip to a wiring plate.
It is another object of the present invention to provide a three-dimensional packaging structure of semiconductor device chips, an elementary unit thereof and a man
REFERENCES:
patent: 3244843 (1966-04-01), Ross
patent: 4117288 (1978-09-01), Gorman et al.
IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mar. 1975, pp. 3084-3086, K. R. Grebe et al.
Aoki Katsuhiko
Kiuchi Kazuhide
Koyabu Kunio
Oohata Masanobu
Sato Yoshiyuki
Macon Robert S.
Nippon Telegraph and Telephone Corporation
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