Three dimensional package and architecture for high performance

Details Three dimensional package and architecture for high performance Three dimensional package and architecture for high performance

1995-11-06

1999-08-10

Evans, Elizabeth

Stock material or miscellaneous articles

Structurally defined web or sheet

Discontinuous or differential coating, impregnation or bond

428209, 428210, 428901, 361784, 174261, B32B 300

Patent

active

059356871

ABSTRACT:
A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The package allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate which has on at least one side thereof at least one integrated circuit device. Between adjacent subassemblies there is disposed a second substrate. There are electrical interconnection means to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies. Optionally, the outer surfaces of the structure that can be disposed a cube of memory chips.

REFERENCES:
patent: 5121299 (1992-06-01), Frankeny
patent: 5239447 (1993-08-01), Cotues
patent: 5299094 (1994-03-01), Nishino
patent: 5316787 (1994-05-01), Frankeny
patent: 5343366 (1994-08-01), Cipolla
patent: 5495397 (1996-02-01), Davidson
Electronic Packaging, Microelectronics and Interconnection Dictionary, Harper, 1994, p. 70.

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