Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1998-07-08
2001-07-31
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S108000, C438S110000, C438S121000
Reexamination Certificate
active
06268238
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a package and architecture which allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds.
BACKGROUND OF THE INVENTION
To reduce the cost and increase the performance or electronic computers, it is desirable to place as many electronic circuits in as small a region as possible in order to reduce the distance over which electrical signals must travel from one circuit to another. This can be achieved by fabricating, on a given area of a semiconductor chip, as many electronic circuits as feasible within a given fabrication technology. These dense chips are generally disposed on the surface of a substrate in a side by side arrangement with space left therebetween to provide regions for electrical conductors for electrical interconnection of the chips. The chip contact locations can be electrically interconnected to substrate contact locations by means of wires bonded in between the chip contact location and substrate contact locations. Alternatively, a TAB tape (which is a flexible dielectric layer having a plurality of conductors disposed thereon) can be used for this electrical interconnection. Alternatively, the semiconductor chips may be mounted in a flip-chip configuration wherein an array of contact locations on the semiconductor chip is aligned with and electrically interconnected to an array of contact locations on a substrate by means of solder mounds disposed between corresponding chips and substrate contact locations. This side by side arrangement of electronic devices is not the most dense configuration which can be achieved.
In the microelectronics industry, integrated circuits, such as semiconductor chips, are mounted onto packaging substrates to form modules. In high performance computer applications, the modules contain a plurality of integrated circuits. A plurality of modules are mounted onto a second level of packages such as a printed circuit board or card. The cards are inserted into a frame to form a computer.
For nearly all conventional interconnection package, except for double sided cards, signals from one chip on the package travel in a two dimensional wiring net to the edge of the package, then travel across the card or board or even travel along cables before they reach the next package which contain the destination integrated circuit chip. Therefore, signals must travel off of one module onto wiring on a board or onto wiring on a cable to a second module and from a second module to the destination integrated circuit chip in the second module. This results in a long package time delay and increases the demands on wireability of the two dimensional wiring arrays.
As the performance requirements of a mainframe computer continue to increase, the signal propagation time for communications from module to module, chip to chip and even device to device become critical. The current solution to this problem is to place the chips as close together as possible on a planar substrate and combine as many circuits as possible onto the substrate using insulators having dielectric constants as low as possible between wiring layers.
However, it is becoming apparent that such solutions will not allow future generation machines to reach the desired performance levels. One of the most significant factors is the time required for a signal to cross the length of a module. Three dimensional packaging structures will overcome the problem of the signal progagation distances in the planar packages, but the difficulty has been finding a suitable way to interconnect the devices in such a structure.
An improvement in chip interconnection propagation time and an increase in real chip packaging density can be achieved if three dimensional wiring between closely spaced planes of chips can be achieved.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved packaging structure wherein the integrated circuit devices are packaged in a three dimensional structure.
It is another object of the present invention to provide such an improved packaging structure with both horizontal electrical interconnections and vertical electrical interconnections.
It is a further object of the present invention to provide an improved packaging structure which is composed of a plurality of subassemblies each of which are separately testable and electrically interconnected by vertical electrical interconnections.
It is yet another object of the present invention to provide an improved packaging structure for providing electrical interconnection to high I/O count chips and providing a means for dissipating heat generated in the chips.
A broad aspect of the present invention is an integrated circuit packaging structure formed from a plurality of subassemblies. Each subassembly has a first substrate having a first side and a second side. There is at least one electronic device disposed on the first side and on the second side. There are a plurality of second substrates. The subassemblies are disposed between the second substrates. The subassemblies are in electrical communication with the second substrates.
In a more particular aspect of the present invention, the first substrates have electrical conductors for providing electrical interconnection between the first and second sides of the first substrate.
In another more particular aspect of the present invention, the electrical conductors of the first substrate predominately provide signal I/O to the electronic devices.
In another more particular aspect of the present invention, the second substrates predominately provide power distribution to the subassemblies.
In another more particular aspect of the present invention, the first substrates have a plurality of contact locations and the second substrates have a plurality of contact locations. Each of the first plurality of contact locations is disposed adjacent one of the second plurality of contact locations. There is an electrical interconnection means between the adjacent contact locations for providing electrical communication between the first substrates and second substrates.
In another more particular aspect of the present invention, each of the second substrates has an end which is disposed in electrical communication with a third substrate.
In another more particular aspect of the present invention, the first plurality of electronic devices and the second plurality of electronic devices are logic devices.
In another more particular aspect of the present invention, a stack of integrated circuit memory devices are disposed in contact with at least one of the second substrates.
REFERENCES:
patent: 5095627 (1992-03-01), Bujagec et al.
patent: 5377077 (1994-12-01), Burns
patent: 5385855 (1995-01-01), Brown et al.
patent: 5789815 (1998-08-01), Tessier et al.
Davidson Evan Ezra
Lewis David Andrew
Shaw Jane Margaret
Viehbeck Alfred
Wilczynski Janusz Stanislaw
Collins D. M.
International Business Machines - Corporation
Morris Daniel P.
Picardat Kevin M.
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