Three-dimensional one-dimensional cell arrangement for dynamic s

Details Three-dimensional one-dimensional cell arrangement for dynamic s Three-dimensional one-dimensional cell arrangement for dynamic s

1990-01-16

1991-06-18

Prenty, Mark

357 54, 357 55, 357 59, H01L 2968, H01L 2934, H01L 2906

Patent

active

050252950

ABSTRACT:
A three-dimensional, one transistor cell arrangement for dynamic semiconductor memories utilizing a trench capacitor in the substrate, and provided with a switching field effect transistor including an insulated gate electrode connected to the source/drain zone, the bit line contact for the connection of the switching transistor being arranged to be self-adjusted on the drain region in the semiconductor substrate, and overlapping the gate electrode with insulating layers on all sides. It also overlaps the neighboring field oxide region. The insulation layer laying beneath the bit line and over the gate level is a triple layer composed of silicon oxide/silicon nitride/silicon oxide, and in the through hole etching which is carried out by specific etching steps, there exists a self-adjusted overlapping contact. By eliminating the imprecision caused by the lithography, the space requirement of a memory cell can be reduced by about 20%. The invention is particularly utilized in the manufacture of 4 megabit DRAMs.

REFERENCES:
patent: 4649625 (1987-03-01), Lu
patent: 4658283 (1987-04-01), Koyama
patent: 4668973 (1987-05-01), Dawson
patent: 4710897 (1987-12-01), Masuoka
patent: 4803535 (1989-02-01), Taguchi
patent: 4894696 (1990-01-01), Takeda et al.
1987 Symposium on VLSI Technology, Digest of Technical Papers, pp. 93 and 94, May 1987, Kuesters et al.
"Cell Structures for Future Dram's", Technical Digest IEDM, 1985, pp. 694 to 697, by Sunami.
"Buried Storage Electrode (BSE) Cell for Megabit Drams", Technical Digest, IEDM, 1985, pp. 710 to 713, by Sakamoto et al.

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