Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1995-06-06
1996-09-03
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257686, 257727, H01L 2302, H01L 23053, H01L 2334
Patent
active
055526330
ABSTRACT:
A three-dimensional array (10) of semiconductor chips (24, 124) includes stacked 2D high density interconnect (HDI) modules (12, 14) held by adhesive (16). Each HDI module has a ceramic substrate (20, 120) with a cavity (22, 122) dimensioned to accommodate a chip. An interconnect sheet (28, 128) has a conductor pattern (30, 130) and vias (32, 132) which interconnect the chips of each HDI module. Thermal conduction from the upper module (12) to the lower module (14) is inhibited by the low thermal conduction of the lower interconnect sheet (128), tending to raise the chip temperature. Thermal conduction is improved by thermally conductive posts (44) extending between upper (20) and lower (120) substrates through apertures (140) in the interconnect sheet (128). If the posts (44) are electrically conductive, they may be used for electrical interconnections among modules of the 3D array.
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Chin G.
Crane Sara W.
Martin Marietta Corporation
Martin Wallace Valencia
Meise W. H.
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