Three-dimensional memory array and method of fabrication

Details Three-dimensional memory array and method of fabrication Three-dimensional memory array and method of fabrication

2001-03-21

2002-07-16

Thompson, Craig (Department: 2813)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

C438S600000

Reexamination Certificate

active

06420215

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the field of vertically stacked field programmable non-volatile memory and method of fabrication.
2. Prior Art
Recently there has been an interest in fabricating memories having memory cells disposed at numerous levels above a substrate. Each level includes a plurality of spaced-apart first lines extending in one direction which are vertically separated from a plurality of parallel spaced-apart second lines in a second direction, for example, extending perpendicular to the first line. Cells are disposed between the first lines and second lines at the intersections of these lines. These memories are described in U.S. Pat. Nos. 5,835,396 and 6,034,882.
As will be seen, the present invention departs from the structures shown in these patents and uses “rail-stacks” as will be described later. The invented memory employs antifuses where a diode is formed upon programming a particular bit. In this connection see, “A Novel High-Density Low-Cost Diode Programmable Read Only Memory, ” by de Graaf, Woerlee, Hart, Lifka, de Vreede, Janssen, Sluijs and Paulzen, IEDM-96, beginning at page 189 and U.S. Pat. Nos. 4,876,220; 4,881,114 and 4,543,594.
SUMMARY OF THE INVENTION
A multi-level memory array disposed above a substrate is disclosed. A first plurality of spaced-apart rail-stacks disposed at a first height and/or a first direction are fabricated above the substrate. Each rail-stack includes a first conductor and a first semiconductor layer extending substantially the entire length of the first conductor. A second plurality of spaced-apart rail-stacks are disposed above the first rail-stacks and run in a second direction different than the first direction. An insulating layer is formed between the first rail-stack and the second conductors which is capable of being selectively breached by passing a current between one of the first and one of the second conductors to program the array.


REFERENCES:
patent: 3913224 (1975-10-01), Preissinger et al.
patent: 4272880 (1981-06-01), Pashley
patent: 4442507 (1984-04-01), Roesner
patent: 4489478 (1984-12-01), Sakurai
patent: 4498226 (1985-02-01), Inoue et al.
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4543594 (1985-09-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5306935 (1994-04-01), Esquivel et al.
patent: 5427979 (1995-06-01), Chang
patent: 5535156 (1996-07-01), Levy et al.
patent: 5745407 (1998-04-01), Levy et al.
patent: 5831325 (1998-11-01), Zhang
patent: 5835396 (1998-11-01), Zhang
patent: 5838530 (1998-11-01), Zhang
patent: 6034882 (2000-03-01), Johnson et al.
Douglas, John H., “The Route to 3-D Chips,”high Technology, vol. 3, No. 9, Sep. 1983, p. 55.
de Graaf, C., “A Novel High-Density Low-Cost Diode Programmable Read Only Memory,” Philips Research Laboratories, Prof. Halstlaan, 4, 5656AA Eindhoven, The Netherlands.

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