Three-dimensional memory

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state

Reexamination Certificate

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C438S600000

Reexamination Certificate

active

07081377

ABSTRACT:
A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.

REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5835396 (1998-11-01), Zhang
patent: 6420215 (2002-07-01), Knall et al.
patent: 6515888 (2003-02-01), Johnson et al.

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