Three-dimensional memory

Semiconductor device manufacturing: process – Making device array and selectively interconnecting

Reexamination Certificate

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Details

C438S131000, C438S600000

Reexamination Certificate

active

06875641

ABSTRACT:
A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.

REFERENCES:
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5835396 (1998-11-01), Zhang
patent: 6420215 (2002-07-01), Knall et al.
patent: 20030003632 (2003-01-01), Cleeves et al.
patent: 20040002186 (2004-01-01), Vyvoda et al.

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