Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-08-09
2004-04-06
Siek, Vuthe (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S109000, C438S127000, C438S128000, C361S735000, C361S813000, C257S678000, C257S686000, C257S693000
Reexamination Certificate
active
06716672
ABSTRACT:
The invention relates to a method of interconnection in three dimensions for packages containing at least one electronic component. It also relates to an electronic device obtained by this method.
The production of current electronic systems, whether civil or military, must take into account the requirements of ever increasing compactness, because of the ever increasing number of circuits involved.
In this search for greater compactness, it has already been proposed to produce stacks of integrated circuit chips or, as described in French patent FR 2 688 630, chip-encapsulating packages, the interconnection being accomplished in three dimensions using the faces of the stack as interconnection surfaces for making the necessary connections between output leads.
The encapsulation of chips in plastic packages, such as for example the standard packages of SOJ (Small Outline J-lead), TSOP (Thin Small Outline Package) or CSP (Chip Scale Package) type has many advantages. Firstly, these packages have been tested and burned-in by the manufacturer, although these operations are very difficult to carry out on bare chips. Moreover, it is generally difficult to obtain bare chips from manufacturers. The combination of these reasons therefore makes it preferential to use packages, which are appreciably less expensive and easier.
The stacking of packages according to the solution of the abovementioned patent involves the following main operations: straightening the output leads in order to facilitate alignment and molding; stacking of the plastic packages; encapsulation with resin and curing; cutting of the block; metalization; etching of the outlines of the connections on the faces of the block. Moreover, since the cutting is carried out on the outside of the packages in order to use the output leads of the packages for the interconnection in three dimensions, the 3D module obtained always has, in the plane of the packages, dimensions greater than the original packages.
The object of the invention is, on the one hand, to simplify the operations of manufacturing a 3D module and, on the other hand, to appreciably reduce the volume occupied. It is based on the idea of cutting the block not any longer on the outside of the packages, but through these packages.
According to the most general aspect of the invention, what is therefore provided is a method of interconnection in three dimensions for at least one package containing at least one electronic component and furnished with connection conductors for connecting, inside said package, connection pads on the component to output leads toward the outside of the package, said method being characterized in that it comprises the following steps:
a) stacking and assembling the elements to be interconnected;
b) cutting through the package or packages, near said components, in order to form a block leaving the cross section of the connection conductors flush;
c) production of the electrical connections between the conductors of the various elements on the faces of said block.
More particularly, for interconnecting several packages together, provision is made for said stacking and assembling step a) to consist in stacking and adhesively bonding the packages.
This method thus dispenses with the operations of straightening the output leads and of encapsulation and curing, the latter being replaced by a simple adhesive bonding operation. The method has thus been simplified.
Moreover, the cutting of the block is carried out near the chips, and therefore through the packages, and no longer on the outside of the packages, hence a reduction of almost 50% in the area of the block in a plane parallel to the packages.
To achieve this solution to the problems of reducing the volume of the electronic devices, it is clear that it was necessary, on the one hand, to go counter to the idea that a package is needed for various functions, namely protection against the external environment, handling not hazardous to the chip and electrical connection to the outside, and must not be cut, and that it was necessary, on the other hand, to state that the transfer molding resins used on the inside of the packages by the semiconductor industry were substantially of the same composition and filler content as the encapsulation resins used in the prior art.
Another, particularly beneficial, application relates to the replacement of complex components rendered obsolete, that is to say no longer available on the market, when, for example, a new series of an old piece of equipment has to be manufactured. During the original design of the equipment, ASIC circuits were able in particular to be defined, which were produced by a supplier who, since then, has changed technology. Hitherto, it was necessary to redevelop a new ASIC. However, there are programmable integrated circuits with a sea of ports, of the FPGA (Field Programmable Gate Array) which would make it possible to program the same functions as the original ASIC circuit. The drawback is that the arrangement, the number of outputs and the dimensions of the ASIC circuit are different from those of the FPGA circuits available: in general, the FPGA circuits, with very large-scale integration, have a substantially larger number of outputs than the ASIC circuit that it would be desired to replace. To produce the functions of an ASIC with 44 outputs for example, only this number of outputs of an FPGA circuit (for example with 144 outputs) would be used. In addition, the arrangement of these outputs will not be the same, hence a mismatch with respect to the card on which this circuit has to be mounted. Finally, there is a risk of the footprint of the FPGA circuit being different and, in general, larger.
The invention makes it possible, through its principle, to solve these problems. According to this new application, provision is made to associate with a complex circuit contained in a package a matching circuit consisting of a printed circuit, of a first array of selection conductors, allowing it to be connected to the suitable outputs of the package, and of a second, matching array, the leads of which reproduce, in terms of number and arrangement, the desired pattern, the printed circuit providing the interconnection between the two arrays.
By implementing the invention, it is thus possible to produce an electronic circuit with interconnection in three dimensions, of small footprint, suitable for the desired application.
This other aspect of the invention therefore provides a method, as generally defined above, for interconnecting a package with a circuit for matching the array of the output leads, characterized in that said stacking and assembly step a) consists in stacking and assembling said matching circuit against said package by adhesive bonding or encapsulation.
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patent: 5400218 (1995-03-01), Val
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patent: 5561591 (1996-10-01), Burns
patent: 5637536 (1997-06-01), Val
patent: 5640760 (1997-06-01), Val et al.
patent: 5847448 (1998-12-01), Val et al.
patent: 5885850 (1999-03-01), Val
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Keshavan Belur V
Siek Vuthe
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