Three dimensional integrated latch and bulk pass transistor for

Details Three dimensional integrated latch and bulk pass transistor for Three dimensional integrated latch and bulk pass transistor for

1995-01-19

1996-06-11

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 74, 257 69, 257903, 36518905, 365188, H01L 29786, H01L 2711

Patent

active

055258140

ABSTRACT:
A three dimensional latch and bulk silicon pass transistor for high density field reconfigurable architectures is provided utilizing bulk silicon with a layer of polysilicon or silicon on insulator (SOI) thereover. The pass transistor, which must have very low resistance to provide a good short circuit path between the metal runs and fast switching speed, is fabricated in the bulk silicon wherein the resistivity can be made very low relative to polysilicon and because only the pass transistor is disposed in the bulk silicon, thereby permitting the dimensions thereof to be increased to provide even lower resistance. Since only the latch is fabricated in the layer of polysilicon or SOI and is disposed over the pass transistor, the amount of chip area utilized can be the same or less than required in the prior art wherein all circuitry was in the bulk silicon. While the resistivity in the polysilicon will be higher than in the bulk silicon, the latch can operate adequately under such conditions of high resistivity since high speed operation thereof is not of importance in the environment in question. The very low resistance path of the pass transistor allows for faster response time than can be obtained in polysilicon for reconfiguration operations.

REFERENCES:
patent: 5086331 (1992-02-01), Hartgring
patent: 5095347 (1992-03-01), Kirsch

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