Three-dimensional integrated circuit package

Details Three-dimensional integrated circuit package Three-dimensional integrated circuit package

1993-02-08

1994-07-05

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361730, 174 522, 174 524, 257686, 257787, H05K 702, H01L 2302

Patent

active

053273257

ABSTRACT:
An integrated circuit package that permits high density packaging of circuit chips. The integrated circuit package has a base substrate support member with an upper and a lower surface. A cavity is located in its upper surface and a similar cavity is located in its lower surface. Two circuit chips are located in each cavity that are connected together in back to back relationship. The cavities are closed or sealed by lids that are bonded to mounting surfaces that are located on the base substrate support member and surround the cavities. A series of terminating leads are located on two sides of the base substrate support member that are electrically connected to the circuit chips. A single cavity embodiment is also set forth that is designed for use when a lesser density is acceptable or desired.

REFERENCES:
patent: 4818821 (1989-04-01), Wentworth et al.
patent: 4827082 (1989-05-01), Horiuchi et al.
patent: 5168126 (1992-12-01), Matsumoto et al.

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