Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2008-06-10
2008-06-10
Williams, Alexander O (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257SE23085, C257SE23114, C257SE25027, C257SE23063, C257SE25023, C257SE23011, C257SE25013, C257SE21597, C257S777000, C257S723000, C257S724000, C257S725000, C257S728000, C257S668000, C257S701000, C257S698000, C257S691000, C257S685000, C257S774000, C257S773000, C438S109000
Reexamination Certificate
active
07385283
ABSTRACT:
A three dimensional integrated circuit structure includes at least first and second devices, each device comprising a substrate and a device layer formed over the substrate, the first and second devices being bonded together in a stack, wherein the bond between the first and second devices comprises a metal-to-metal bond and a non-metal-to-non-metal bond.
REFERENCES:
patent: 3343256 (1967-09-01), Smith et al.
patent: 3372070 (1968-03-01), Zuk
patent: 3648131 (1972-03-01), Stuby
patent: 3787252 (1974-01-01), Filippazzi et al.
patent: 5111278 (1992-05-01), Eichelberger
patent: 5528080 (1996-06-01), Goldstein
patent: 5618752 (1997-04-01), Gaul
patent: 5646067 (1997-07-01), Gaul
patent: 5682062 (1997-10-01), Gaul
patent: 5814889 (1998-09-01), Gaul
patent: 5973396 (1999-10-01), Farnworth
patent: 6355976 (2002-03-01), Faris
patent: 6459150 (2002-10-01), Wu et al.
patent: 6469374 (2002-10-01), Imoto
patent: 6489676 (2002-12-01), Taniguchi et al.
patent: 6548891 (2003-04-01), Mashino
patent: 6614095 (2003-09-01), Adamschik et al.
patent: 6642081 (2003-11-01), Patti
patent: 6897125 (2005-05-01), Morrow et al.
patent: 6982487 (2006-01-01), Kim et al.
patent: 7157787 (2007-01-01), Kim et al.
patent: 7179740 (2007-02-01), Hsuan
patent: 2004/0214387 (2004-10-01), Madurawe
patent: 2005/0127478 (2005-06-01), Hiatt et al.
patent: 2005/0215054 (2005-09-01), Rasmussen et al.
patent: 2007/0045780 (2007-03-01), Akram et al.
Daniel Radack, “3D Microsystems”, DARPA Microsystems Technology Office, 32 pages.
Subhash Gupta et al., “Techniques for Producing 3D ICs with High-Density Interconnect”, 5 pages.
J.-Q. Lu et al., “Evaluation Procedures for Wafer Bonding and Thinning of Interconnect Test Structures for 3D ICs”, 3 page.
A. Fan et al., “Copper Wafer Bonding”, pp. 534-536.
K. W. Guarini et al., Electrical Integrity of State-of-the-Art 0.13 um SOI CMOS Devices and Circuits Transferred for Three-Dimensional (3D) Integrated Circuit (IC) Fabrication, 2002 IEEE, pp. IEDM 943-945.
Shamik Das et al., Calibration of Rent's-Rule Models for Three-Dimensional Integrated Circuits, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 12. No. 4. Apr. 2004. pp. 359-366.
Shamik Das et al., “Technology, Performance, and Computer-Aided Design of Three-Dimensional Integrated Circuits”, ISPD '04 Apr. 18-21, 2004, 8 pages.
Shinya Ito et al., “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, 2000 IEEE, pp. IEDM 00-247-IEDM 250.
Chiou Wen-Chih
Wu Weng-Jin
Duane Morris LLP
Taiwan Semiconductor Manufacturing Co. Ltd.
Williams Alexander O
LandOfFree
Three dimensional integrated circuit and method of making... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Three dimensional integrated circuit and method of making..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three dimensional integrated circuit and method of making... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2809831