Three-dimensional integrated circuit

Details Three-dimensional integrated circuit Three-dimensional integrated circuit

1986-07-07

1988-10-18

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 22, 357 47, 357 49, 357 50, 357 58, 307450, H01L 2702, H01L 2912, H01L 2980

Patent

active

047791276

ABSTRACT:
In order to minimize the interconnections, there is provided a three-dimensional integrated circuit fabricated on a semi-insulating substrate of compound semiconductor material comprising a first compound semiconductor layer formed on the surface of the semi-insulating substrate and electrically connected to a variable voltage source, a second compound semiconductor layer formed on the surface of the first compound semiconductor layer opposite in conductivity type thereto and providing an electric device together with the first compound semiconductor layer, an undoped compound semiconductor layer epitaxially grown on the surface of the second compound semiconductor layer and formed with a plurality of doped regions for providing interconnections of the three dimensional integrated circuit, one of the interconnections providing an electric connections to the electric device formed with the first and second compound semiconductor layers, a doped compound semiconductor layer formed on the surface of the undoped compound semiconductor layer and capable of providing a current path established therein, and a conductive layer formed on the surface of the doped compound semiconductor layer and providing a gate to control the current path in the doped compound semiconductor layer, the conductive layer and the doped compound semiconductor layer forming parts of a field effect transistor which in turn forms parts of the three-dimensional integrated circuit together with the electric device.

REFERENCES:
patent: 4351099 (1982-09-01), Tagaki et al.
patent: 4490632 (1984-12-01), Everett et al.
Elect. Comm. Soc. Papers, vol. 66, No. 8, pp. 831-834, Aug. 1983.
IEEE Elect. Dev. Lettrs., vol. EDL-5, No. 11, Nov. 1984, "Folded Gate-A Novel Logic Gate Structure", Shur.
IEEE GaAs IC Symposium Digests, 1984, pp. 121-124, Ishii et al., "Processing . . . LSIs".

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