Three-dimensional integrated capacitance structure

Details Three-dimensional integrated capacitance structure Three-dimensional integrated capacitance structure

2007-01-09

2007-01-09

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257S499000, C257S528000, C257SE29001

Reexamination Certificate

active

11321554

ABSTRACT:
A three-dimensional integrated capacitance structure comprises at least two arrays of “unit cells” on respective layers of an IC, with each unit cell comprising a center conductor and a conducting ring which surrounds the center conductor. Each array comprises a plurality of unit cells, tiled on a given IC layer at a predetermined pitch. The arrays are arranged vertically such that adjacent vertical arrays are offset in the x and y dimensions by a predetermined fraction—preferably ½—of the unit cells' pitch. The structure includes vias arranged to interconnect the arrays such that each center conductor is connected to a conducting ring of the array immediately above and/or below the center conductor, and such that each conducting ring is connected to a center conductor of the array immediately above and/or below the conducting ring.

REFERENCES:
patent: 5208725 (1993-05-01), Akcasu
patent: 5978206 (1999-11-01), Nishimura et al.
patent: 6178083 (2001-01-01), Appeltans et al.
patent: 6963122 (2005-11-01), Soenen et al.

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