Patent
1991-04-19
1992-11-10
Herndon, Heather R.
395120, G06F 3153
Patent
active
051631270
ABSTRACT:
A three-dimensional graphic processing apparatus includes n arithmetic ICs (Integrated Circuits) for performing linear interpolation calculations for each scan line of a triangle polygon to obtain intensity values and depth coordinate values of pixels, and two types of n memories for storing the calculation results. The n arithmetic ICs parallelly execute linear interpolation calculations of n different pixels successive on a single scan line of a single triangle polygon in one processing cycle. Each arithmetic IC calculates for each of every n pixels in one processing cycle, and a corresponding one of the memories stores the calculation result.
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D. Fussell et al., A VLSI-Oriented Architecture for Real-Time Raster Display of Shaded Polygons, May 17, 1982, Graphics Interface '82, pp. 376-377.
Aikawa Takeshi
Ikumi Nobuyuki
Ohhashi Masahide
Saito Mitsuo
Herndon Heather R.
Kabushiki Kaisha Toshiba
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