Three dimensional famos memory devices and methods of fabricatin

Details Three dimensional famos memory devices and methods of fabricatin Three dimensional famos memory devices and methods of fabricatin

1992-12-14

1995-01-03

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 437 52, 437 56, 437 59, H01L 2978, H01L 2710

Patent

active

053792556

ABSTRACT:
Memory cell transistors are provided in which pillar structures or column structures (12, 12a, 14, and 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the pillar structures or column structures (12, 12a, 14, and 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36, 40, and 48) are implanted in the semiconductor substrate (10). Drain regions (38) are also implanted in the pillar structures or column structures (12, 12a, 14 and 14a).

REFERENCES:
patent: 5001526 (1991-03-01), Gotou
K. Sunouchi et al., "A Surrounding Gate Transistor(SGT) Cell for 64/256Mbit DRAMS", IEEE, IEDM 1989, pp. 2.1.1-2.1.4, (23-26).

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