Three-dimensional direct-write EEPROM arrays and fabrication met

Details Three-dimensional direct-write EEPROM arrays and fabrication met Three-dimensional direct-write EEPROM arrays and fabrication met

1992-03-12

1995-11-14

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

365149, 365195, 257298, 257302, 257319, 257320, G11C 1400

Patent

active

054673054

ABSTRACT:
A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

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Terada et al. "High-Speed Page Mode Sensing Scheme for EEPROM's and Flash EEPROM's using Divided Bit Line Architecture", 1990 Symposium on VSLI Circuits IEEE, pp. 97-98, 1990.
Yamauchi et al., "A 4M Bit NVRAM Technology Using a Novel Stacked Capacitor on Selectively Self-Aligned Flotox Cell Structure", IEDM, pp. 931-933, 1990.

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