Three-dimensional direct-write EEPROM arrays and fabrication met

Details Three-dimensional direct-write EEPROM arrays and fabrication met Three-dimensional direct-write EEPROM arrays and fabrication met

1995-06-05

1997-04-01

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular connection

36518501, 36518508, 365149, 365195, 36518514, 257298, 257302, 257319, 257320, G11C 1604

Patent

active

056173512

ABSTRACT:
A three-dimensional memory cell, suitable for electrically erasable programmable read only memories (EEPROMS), which has direct-write cell capability is disclosed. The memory cell is utilized in the fabrication of non-volatile, direct-write EEPROM arrays with high integration density. A typical EEPROM array includes a plurality of elongated shallow trenches formed in a semiconductor substrate. Multiple direct-write EEPROM cells are disposed within each elongated trench such that each EEPROM cell shares a recall gate and a program gate with another cell in the same trench. Preferably, a silicon rich dielectric (such as silicon rich oxide) disposed between each floating gate and its associated programming and recall gates. Both common source diffusion and isolated source diffusion embodiments are disclosed. Further, various fabrication methods for the direct-write EEPROM arrays presented are described.

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Y. Yamauchi et al., "A 4Mbit NVRAM Tech. Using a Novel Stacked Cap. on Sel. Self-Align. Flotox Cell Str.," 1990 I.E.O.M., pp.931-933.
Y. Terada et al., "High Speed Page Mode Sens. Sch. for EPROM's and Flash EEPROMs Using Divided Bit Line Arch.," 1990 Symp. on VLSI Crts, pp. 97-98.

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