Three-dimensional die-stacking package structure

Details Three-dimensional die-stacking package structure Three-dimensional die-stacking package structure

2011-03-08

2011-03-08

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S782000, C257S778000, C257SE23067, C438S109000, C438S110000, C438S113000

Reexamination Certificate

active

07902674

ABSTRACT:
This invention provides a substrate having at least one bottom electrode formed therein. A plurality of dice each having at least one opening formed therein are vertically stacked together one by one by a polymer insulating layer acting as an adhering layer between them, along with the openings thereof aligned to each other to form a through hole passing through said dice. The stacked dice are joined to a bottom of the substrate with the polymer insulating layer acting as an adhering layer, making the bottom electrode of the substrate contact the through hole. An electroplating process is performed with the bottom electrode serving as an electroplating electrode to form a conductive contact passing through the dice.

REFERENCES:
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patent: 6429096 (2002-08-01), Yanagida
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patent: 6815046 (2004-11-01), Mandai et al.
patent: 7598617 (2009-10-01), Lee et al.
patent: 2005/0230804 (2005-10-01), Tanida et al.
patent: 2005/0263869 (2005-12-01), Tanaka et al.

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