Three-dimensional CMOS using selective epitaxial growth

Details Three-dimensional CMOS using selective epitaxial growth Three-dimensional CMOS using selective epitaxial growth

1986-01-02

1987-08-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

357 231, 357 233, 357 239, 357 55, 357 46, 437 56, 437 89, H01L 2978, H01L 2702, H01L 2904

Patent

active

046867589

ABSTRACT:
A three-dimensional CMOS integrated circuit structure in which two complementary field effect transistors are fabricated in vertical alignment with one another, and in which both transistors are single crystal and share a common crystal lattice structure and form a single unitary crystalline structure.

REFERENCES:
patent: 4241359 (1980-12-01), Izumi et al.
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4476475 (1984-10-01), Naem et al.
patent: 4479297 (1984-10-01), Mizutani et al.
Colinge et al., IEDM, Wash. D.C. USA, Dec. 7-9, 1981, "ST-CMOS . . . Technology", pp. 557-560.
Douglas, High Technology, Sep. 1983, "The Route to 3-D Chips, pp. 55-59.

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