Three-dimensional chip-stack synchronization

Details Three-dimensional chip-stack synchronization Three-dimensional chip-stack synchronization

2011-01-04

2011-01-04

Luu, An T (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S295000, C327S565000

Reexamination Certificate

active

07863960

ABSTRACT:
A central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews.

REFERENCES:
patent: 5760478 (1998-06-01), Bozso et al.
patent: 6040203 (2000-03-01), Bozso et al.
patent: 6526112 (2003-02-01), Lai
patent: 7538603 (2009-05-01), Ikeda et al.

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