Three-dimensional array of re-programmable non-volatile...

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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C365S130000, C365S135000, C365S154000, C365S180000, C365S182000

Reexamination Certificate

active

07983065

ABSTRACT:
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

REFERENCES:
patent: 3448302 (1969-06-01), Shanefield
patent: 4583201 (1986-04-01), Bertin et al.
patent: 4805142 (1989-02-01), Bertin et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5172338 (1997-07-01), Mehrotra et al.
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5894437 (1999-04-01), Pellegrini
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6373746 (2002-04-01), Takeuchi et al.
patent: 6456528 (2002-09-01), Chen
patent: 6522580 (2003-02-01), Chen et al.
patent: 6538922 (2003-03-01), Khalid et al.
patent: 6643188 (2003-11-01), Tanaka et al.
patent: 6664639 (2003-12-01), Cleeves
patent: 6678192 (2004-01-01), Gongwer et al.
patent: 6771536 (2004-08-01), Li et al.
patent: 6781877 (2004-08-01), Cernea et al.
patent: 6870755 (2005-03-01), Rinerson et al.
patent: 7023739 (2006-04-01), Chen et al.
patent: 7177191 (2007-02-01), Fasoli et al.
patent: 7221588 (2007-05-01), Fasoli et al.
patent: 7237074 (2007-06-01), Guterman et al.
patent: 7324393 (2008-01-01), Chan et al.
patent: 7339812 (2008-03-01), Nejad et al.
patent: 7342279 (2008-03-01), Harari et al.
patent: 7382647 (2008-06-01), Gopalakrishnan
patent: 7456460 (2008-11-01), Burr et al.
patent: 2003/0103377 (2003-06-01), Kajiyama
patent: 2003/0206481 (2003-11-01), Hsu et al.
patent: 2004/0057276 (2004-03-01), Nejad et al.
patent: 2004/0151024 (2004-08-01), Fricke et al.
patent: 2004/0159868 (2004-08-01), Rinerson et al.
patent: 2004/0264244 (2004-12-01), Morimoto
patent: 2005/0045919 (2005-03-01), Kaeriyama et al.
patent: 2005/0128807 (2005-06-01), Chen et al.
patent: 2006/0184720 (2006-08-01), Sinclair et al.
patent: 2006/0250837 (2006-11-01), Herner et al.
patent: 2007/0133268 (2007-06-01), Choi et al.
patent: 2007/0252201 (2007-11-01), Kito et al.
patent: 2008/0002461 (2008-01-01), Rinerson et al.
patent: 2008/0006812 (2008-01-01), Kozicki et al.
patent: 2008/0084729 (2008-04-01), Cho et al.
patent: 2008/0175031 (2008-07-01), Park et al.
patent: 2008/0175032 (2008-07-01), Tanaka et al.
patent: 2008/0239790 (2008-10-01), Herner et al.
patent: 2009/0001342 (2009-01-01), Schricker et al.
patent: 2009/0001344 (2009-01-01), Schricker et al.
patent: 2009/0027950 (2009-01-01), Lam et al.
patent: 2009/0085153 (2009-04-01), Maxwell et al.
patent: 2010/0259961 (2010-10-01), Fasoli et al.
patent: 2010/0259962 (2010-10-01), Yan et al.
patent: 1 796 103 (2007-06-01), None
patent: WO 2009/011221 (2009-01-01), None
Chen et al., “Ultra-Thin Phase-Change Bridge Memory Device Using GeSb,” 1-4244-0439-8/06, IEEE International Electron Devices Meeting, Aug. 2006, 4 pages.
Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” IEEE, Aug. 2006, 1-4244-0439-8/06, 4 pages.
Kaeriyama et al., “A Nonvolatile Programmable Solid-Electrolyte Nanometer Switch,” IEEE Journal of Solid-State Circuits, vol. 40, No. 1, Jan. 2005, pp. 168-176.
Kozicki et al., “Multi-bit Memory Using Programmable Metallization Cell Technology,” Proceedings of the International Conference on Electronic Devices and Memory, Grenoble, France, Jun. 12-17, 2005, 3 pages.
Kozicki et al., “Programmable Metallization Cell Memory Based on Ag-Ge-S ans Cu-Ge-S Solid Electrolytes,” IEEE, Sep. 2005, 0-7803-9408-9/05, pp. 83-89.
Kreupl et al., “Carbon-Based Resistive Memory,” 2008 IEEE International Electron Device Meeting, San Francisco, Dec. 15-17, 2008, pp. 1-4.
Kund et al., “Conductive bridging Ram (CBRAM): An emerging non-volatile memory technology scalable to sub 20nm,” IEEE, Aug. 2005, 0-7803-9269-8/05, 4 pages.
Numonyx™, “The basics of phase change memory (PCM) technology. A new class of non-volatile memory.” http://www.numonyx.com/en-US/ResourceCenter/Pages/WhitePapers.aspx, 5 pages, Sep. 1970.
Sakamoto et al., “A Ta2O5solid-electrolyte switch with improved reliability,” 2007 Symposium on VLSI Technology Digest of Technical Papers, 978-4-900784-03-1, pp. 38-39.
Schrogmeier et al., “Time Discrete Voltage Sensing and Iterative Programming Control for a 4F2Multilevel CBRAM,” 2007 Symposium on VLSI Technology Digest of Technical Papers, 978-4-900784-04-8, pp. 186-187.
Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” 2007 Symposium on VLSI Technology Digest of Technical Papers, 978-4-900784-03-1, pp. 14-15.
Williams, “How we found the missing Memristor. The memristor—the functional equivalent of a synapse—could revolutionaze circuit design,” IEEE Spectrum, Dec. 2008, pp. 28-35.
Yang et al., “Memristive switching mechanism for metal/oxide/metal nanodevices,” Published online on Jun. 15, 2008, 2008, Macmillian Publishers Limited, Nature nanotechnology, vol. 3, Jul. 2008, www.nature.com
aturenanotechnology, pp. 429-433.
Yoon et al., “Vertical Cross-point Resistance Change Memory for Ultra-High Density Non-volatile Memory Applications,” 2009 Symposium on VLSI Technology Digest of Techincal Papers, 2009 Symposium on VLSI in Kyoto, Japan, Jun. 15, 2009, 2 pages.
ISA/EPO, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2010/029852, mailed on Nov. 24, 2010, 36 pages.
EPO/ISA, “Invitation to Pay Additional Fees,” corresponding International Patent Application No. PCT/US2010/029852, mailed on Jul. 2, 2010, 8 pages.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2010/029855, mailed on Jul. 21, 2010, 20 pages.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration,” corresponding International Patent Application No. PCT/US2010/029857, mailed on Jul. 28, 2010, 19 pages.

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