Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
2002-06-19
2003-12-09
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C712S229000
Reexamination Certificate
active
06662204
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a thread control system and a method for an operating system used in a computer system and more particularly to a system and a method for monitoring and controlling threads having such a high priority as to impede the execution of the operating system.
In the event where an operating system of a computer system runs into any abnormal operation, the computer system is recovered by an additional hardware such as a watchdog timer and a recovery processing program that is triggered to operate by the time over of a watchdog timer. On the other hand, if an application program runs into trouble of an endless loop during its execution, a CPU may be unreasonably occupied by the program. This kind of trouble is not detectable by a watchdog timer because the interruption process of an operation system is properly executed.
So far, in a computer system, except for the interruption process requiring a high priority, an operating system (hereinafter, referred to as OS) is impeded when a program is in trouble, if too high priority to impede OS is given to the program. For this reason, the computer system might possibly be disabled to operate.
To solve this problem, insufficient measures shown below were so far taken.
(1) No excessively high priority is given.
(2) While being well aware of the risk, high priorities are given.
However, when it was desired to make a response time short, it was not achieved to make a response time short by the above-mentioned measure (1). Further, with the above-mentioned measure (2), the operations of systems including other application software (hereinafter, referred to as application) could not be continued, if the systems should be in trouble. Therefore, the risk was high.
In particular, if a thread having a fixed priority is in such a trouble as the endless loop, the operation of other applications or threads required for systems can be impeded. However, when viewed from the OS, it does not regard the operation as abnormal by judging that the operation is properly executed because no error is detected. It has been, therefore, a general practice to use a fixed priority on the user's responsibility.
BRIEF SUMMARY OF THE INVENTION
The present invention has been made in order to solve the existing problems described.
It is an object to provide a thread control unit in a computer system for supervising of threads and for controlling a priority which enables to give the thread such high priorities as to impede the execution of an OS.
According to the present invention, high priorities with which the operation of an OS can be impeded are given to threads for an application (A thread is a basic unit for the execution of an application. An application comprises more than one thread.). The status of threads is supervised at a regular interval. Even if a thread for the application is in trouble and a CPU is occupied, thus impeding the operation of an OS, a computer system is protected by detecting a thread that is operating abnormally and lowering a priority of that thread temporarily. Thus, it becomes possible to protect a computer system and other applications when a CPU is occupied by the abnormal operation of threads.
Further, according to the present invention, even if a priority of a thread is lowered temporarily, the lowered priority is restored to the pre-set original priority with a judgment that the thread becomes normal again, when a CPU is allocated in the next time and is then abandoned voluntarily for waiting an event.
In order to achieve the above-mentioned object in a thread control of an operating system for a computer system having one or more CPUs, an interruption signal is generated by a timer that counts for a specified time period. Then the thread executed by said CPU is checked when said interruption signal is received. The thread that is confirmed to be executing by the check is stored in the executing thread memory. The thread checked now is judged whether it is the same thread as checked last time and stored in said executing thread memory. When they are the same thread, a value of a counter that counts the number of thread checks is incremented. When the value of the counter is in excess of a specified value, it is judged that an applicable thread is operating abnormally. Then, a priority of the abnormal thread is force to be lowered to a priority that does not affect said operating system. When a CPU is allocated, thereafter, to the thread with a low priority, the priority is restored to the original higher priority, if the thread returned to the normal state by the execution of other tasks.
According to the present invention, whether a thread is in the normal state or not is judged by whether the thread abandons a CPU voluntarily for waiting an event or not. In other words, with respect to a thread which was judged to be abnormal as it occupied a CPU the priority of which was lowered, its priority is restored to the original one when the thread is waiting for an event.
According to the present invention, it is possible to avoid the abnormal state by temporarily lowering a priority of a thread that is occupying a CPU unreasonably.
Further, according to the present invention, user is able to terminate an abnormal thread. For instance, user is able to terminate a thread and process by lowering a priority of a thread against the abnormal operation caused by an unavoidable logical bug. Thus, it is possible to safely shut down a computer system.
REFERENCES:
patent: 5513319 (1996-04-01), Finch et al.
patent: 5515538 (1996-05-01), Kleiman
patent: 5845117 (1998-12-01), Fujita
patent: 6006249 (1999-12-01), Leong
patent: 6085215 (2000-07-01), Ramakrishnan et al.
patent: 6085218 (2000-07-01), Carmon
patent: 6105048 (2000-08-01), He
patent: 6182238 (2001-01-01), Cooper
patent: 6298410 (2001-10-01), Jayakumar et al.
patent: 6360243 (2002-03-01), Lindsley et al.
patent: 99/21081 (1999-04-01), None
Chen et al Optimized Multiple Performance Criteria for Redundant Manipulators by Sub Task Priority Control, pp. 2534-2539, IEEE 1996.
Hasegawa Yoshiaki
Watakabe Takeshi
Donaghue Larry D.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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