Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
2000-03-27
2002-04-09
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S424000, C438S353000, C438S296000
Reexamination Certificate
active
06368931
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor fabrication, and, more specifically, the present invention relates to the fabrication of isolation structures. In particular, the present invention relates to the fabrication of shallow trench isolation structures.
2. Description of Related Art
In the fabrication of semiconductor isolation trench structures, processing is carried out to prevent problems that become more pronounced as miniaturization progresses. One such problem occurs in the 0.13 micron geometry processing regime, and at smaller geometries. At these geometries, a high-density plasma (HDP) physical vapor deposition (PVD) shallow trench fill process may be necessary to get a trench to properly fill. Unfortunately, the requisite HDP PVD conditions result in a compressive stress within the trench that is damaging to the semiconductive channel that it borders. The stress is presumed to cause an unacceptable decrease in the maximum drive current of the device. This decrease in the maximum drive current is presumed to be caused by lattice disruptions that result from the compressive stress. Under such conditions, an isolation trench filled with this compressive material exhibits destructive or damaging compression of the transistor channel. For example, an n-metal oxide silicon (NMOS) transistor experiences degradation of the NMOS transistor performance metrics such as mobility.
One proposed solution is to form the trench fill under conditions that make the material less compressive. However, this solution may create an unacceptable trade-off that results in an unfilled trench and possibly in losing favorable wet-etch, edge leakage, and polish performance of the more compressive HDP PVD shallow trench fill recipes.
Another problem is the formation of sharp top corners at the precipice of the trench in the silicon substrate. Sharp corners of the trench may carry stronger electromagnetic fields that may cause problems when later forming active regions on either side of the trench. For example, when forming a transistor adjacent to the trench a gate insulating oxide layer is grown over the substrate and over the trench, because of the sharp corners, the gate oxide layer cannot be grown with a uniform thickness because it becomes too thin over the sharp corners. The thin gate oxide layer may break down if subjected to high electromagnetic field.
Sharp top corners also cause a problem when filling the trench. As stated above, the trench is generally filled using HDP CVD techniques that fill the trench with materials such as an oxide, polysilicon, or a combination thereof. HDP CVD processes subject the structure to plasma that also induces an electric field around the sharp corners that causes a non-uniform deposition process and that may create gaps or voids in the trench fill.
What is needed is a method of shallow trench formation that overcomes the problems of the prior art.
REFERENCES:
patent: 5780346 (1998-07-01), Arghavani et al.
patent: 5827769 (1998-10-01), Aminazadeh et al.
patent: 6037237 (2000-03-01), Park et al.
patent: 6090714 (2000-07-01), Jang et al.
Hu. S.M. “Stress related problems in silicon Technology,” J. Appl. Phys., 70 (6), Sep. 15, 1991, R53.
Kuroi, T et al., “Stress analysis of shallow trench isolation for 256DRAM and beyond,” IEDM Tech. Dig. 1998.
Saino, K., et al., “Control of trench sidewall stress in bias ECR-CVD oxide filed STI for enhanced DRAM data retention time,” IEDM Tech. Dig. 1998.
Smeys, P, et al., “Influence of process-induced stress on device characteristics and its impact on scaled device performance,” IEEE Trans. on Elec. Dev., 46(6) Jun. 1999, 1245-1251.
Scott, G. et al., “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation induced Stress”, IEDM Tech. Dig. 1999.
Steegen, A., “Silicide induced pattern density and orentation dependent transconductance in MOS transistors,” IEDM Tech. Dig. 1999.
Hamada, A., et al., A new aspect of mechanical stress effects in scaled MOS devices, IEEE Trans. on Elec. Dev., 38(4) Apr. 1991, 895-900.
Sze, S., Semiconductor Sensors, ed. Wiley. N.Y. pp. 162-3, 1994.
M.E. Law et al., “Continuum based modeling of silicon integrated circuit processing: An object oriented approach,” Computational Materials Science, 12, 1998, 289-308.
Stiffler, S.R., “Oxide-induced substrate strain in advanced silicon integrated-circuit fabrication,” Appl. Phys. 68(1), Jul. 1, 1990, 351-355.
Kuhn Kelin J.
Post Ian R.
Everhart Caridad
Intel Corporation
LandOfFree
Thin tensile layers in shallow trench isolation and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin tensile layers in shallow trench isolation and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin tensile layers in shallow trench isolation and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2930696