Thin SOI layer for fully depleted field effect transistors

Details Thin SOI layer for fully depleted field effect transistors Thin SOI layer for fully depleted field effect transistors

1992-12-16

1993-11-23

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 21, 437 61, 437966, H01L 21465

Patent

active

052643956

ABSTRACT:
A method of forming a SOI integrated circuit includes defining thin silicon mesas by etching a device layer down to the underlying insulator, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature PECVD process, with nitride sidewalls on the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000.ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.

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