Thin, small-sized power semiconductor package

Details Thin, small-sized power semiconductor package Thin, small-sized power semiconductor package

2001-07-02

2003-09-16

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S690000, C257S718000, C257S778000, C257S779000, C257S780000

Reexamination Certificate

active

06621152

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a thin, small sized power semiconductor package.
2. Description of the Related Art
Recently, the size of electronic products such as personal computers, cellular phones, and camcorders, is becoming smaller, whereas the capacity of electronic products is becoming larger. Accordingly, chips used in electronic products should be small in size and large in capacity. Besides, a small-sized semiconductor package having a large capacity, which is appropriate even for high processing speeds, is necessary. Chips in a semiconductor package are protected from outside shock, and the chips should be conveniently and securely mounted on a board. Further, a power semiconductor package to which a high voltage is applied should have excellent thermal performance that quickly dissipates heat generated in the chips.
Hereinafter, a semiconductor package according to the prior art will be described with reference to the attached drawings.
A semiconductor package shown in
FIGS. 1A through 1C
is a quad flat no-lead (QFN) package registered in international standards (JEDEC-MO-220) in 2000. The QFN package is a well-known traditional package of reduced size.
FIG. 1A
is a perspective view of a conventional QFN package, and for the convenience of explanation, the bottom of the package faces upward.
FIG. 1B
is a plan view of the QFN package, and
FIG. 1C
is a sectional view of the QFN package mounted on a board.
Referring to
FIGS. 1A through 1C
, a chip
1
is bonded to a die pad
11
of a lead frame by an adhesive
7
. Bonding wires
5
electrically connect bond pads
1
a
of the chip
1
to leads
9
. The chip
1
, the bonding wires
5
, the die pad
11
, and the leads
9
are molded by a molding material
3
. The leads
9
are bonded to a solder paste
13
, and thus a QFN package
50
is mounted on a board
60
.
A lot of heat is generated in a chip
1
, especially, in a power semiconductor chip, when the chip
1
is operated. Heat can cause a malfunction of internal devices. Thus, a power semiconductor package should have excellent thermal performance so that the heat may be quickly dissipated away from the power semiconductor QFN package
50
. The chip
1
is mounted only on the die pad
11
of the lead frame and is not mounted on the leads
9
of the lead frame. Thus, the heat generated from the chip
1
is conducted to the die pad
11
by the adhesive
7
. Preferably, the heat conducted to the die pad
11
is quickly dissipated by ground wiring (not shown) formed on the board
60
under the package
50
. The reason why the heat is dissipated by the ground wiring is that heat flows through a conductive material faster than it flows through a molding material. However, in the conventional package shown in
FIG. 1C
, an exposed die pad
11
a
is not connected to the ground wiring (not shown) of the board
60
and is surrounded by the peripheral leads
9
. Thus, it is difficult for the heat conducted to the exposed die pad
11
a
to be dissipated via the ground wiring and air.
The chip
1
, the bonding wire
5
, the die pad
11
, and the leads
9
are molded by the molding material
3
. An external connection terminal
9
a
of the leads
9
must be not molded by the molding material
3
so that the leads
9
electrically connected to the bonding pad
1
a
of the chip
1
may be connected to the board
60
outside of the QFN package
50
. The external connection terminal
9
a
is bonded to the solder paste
13
and exchanges electrical signals with the board
60
. For the purpose of reliable exchange of electrical signals between the chip
1
of the QFN package
50
and the board
60
, the external connection terminal
9
a
must be exactly fixed in the board
60
. However, since the external connection terminal
9
a
is flat, if the QFN package
50
is mounted incorrectly on the board
60
, the area where is bonded and fixed by the solder paste
13
is reduced and mounting property of the QFN package
50
is lowered.
The QFN package
50
must not detach from the solder paste
13
even if there is some vibration, motion, or shock to the QFN package
50
. However, since the external connection terminal
9
a
is flat, stress caused by shock to the QFN package
50
is not alleviated and is transmitted to the solder paste
13
. Thus, the solder joint is less reliable.
Grooves
17
are formed on lower portions of the leads
9
and the die pad
11
so that the leads
9
and the die pad
11
do not detach from the QFN package
50
after the molding material
3
is molded. As shown in
FIG. 1C
, the grooves
17
are formed only by an etched lead frame. Since the etched lead frame is manufactured using an etching solution in a one-time etching process, the manufacturing cost is high, and it takes much time to manufacture the etched lead frame. Thus, the etched lead frame is not appropriate for the QFN package.
Another method for manufacturing the lead frame includes a stamping process. Mass production of the stamped lead frame is possible, and the manufacturing cost is low. Thus, in order to reduce the manufacturing cost of the QFN package, it is preferable to manufacture a lead frame by the stamping process. However, only the etched lead frame is used as the lead frame of the QFN package
50
.
The die pad
11
of the QFN package
50
is larger than the chip
1
. The adhesive
7
is bonded on the entire bottom surface of the chip
1
to join the chip
1
and the die pad
11
to each other. The adhesive
7
is a paste including, for example, silver (Ag). When the size of the chip
1
becomes large, the size of the die pad
11
must become large. Thus, the lead frame must be re-manufactured according to the size of the chip
1
.
The QFN package
50
can be molded by a block mold type and undergo a sawing process or by an individual mold type and undergo a trimming process. In the case of the block mold type using the sawing process for singularization of the QFN package
50
, a burr remains in a side part
9
b
of the leads
9
after sawing. In the case of the individual mold type, the burr does not occur. But, since a mold die frame must be manufactured according to the size of the QFN package, manufacturing cost of the QFN package is increased.
FIG. 2
is a sectional view of a side pad-bottom lead package (S-BLP) mainly used at an industrial site. The S-BLP is a package applied in the structure in which a bonding pad is formed around a chip. The chip
1
is mounted on leads
10
and is bonded to the leads
10
by an adhesive tape
8
bonded to part of the bottom surface of the chip
1
. Also, one end of the leads
10
toward the side of a S-BLP
52
are surrounded by molding material
3
above and below. Thus, in a case where the S-BLP
52
is singularized by the block mold type, the burr does not occur in the ends of the leads
10
.
Since the chip
1
and the leads
10
are bonded by the adhesive tape
8
and the heat conductivity of the adhesive tape
8
is poor, the adhesive tape
8
is not soft enough for motion such as oscillation. Thus, thermal performance and solder joint reliability are lessened.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a thin, small-sized power semiconductor package, which is capable of improving solder joint reliability, mounting property, and thermal performance and reducing package size.
To achieve the above object, according to a first preferred embodiment of the present invention, there is provided a power semiconductor package. The power semiconductor package includes a plurality of leads each having a groove, a chip mounted on the leads, a plurality of conductive media for electrically connecting the leads to the chip, and a molding material. The groove is arranged along a side of the chip such that the inner surface of the groove faces the chip, and the molding material molds the chip, the leads, and the conductive media so that part of an outer surface of the groove is e

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