Thin silicon based substrate

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S774000, C257S621000, C257SE23063, C257SE23067, C438S618000, C438S624000

Reexamination Certificate

active

07443030

ABSTRACT:
Embodiments of the invention provide a device with a die and a substrate having a similar coefficient of thermal expansion to that of the die. The substrate may comprise a silicon base layer. Build up layers may be formed on the side of the base layer further from the die.

REFERENCES:
patent: 3842189 (1974-10-01), Southgate
patent: 4642889 (1987-02-01), Grabble
patent: 5321583 (1994-06-01), McMahon
patent: 5350886 (1994-09-01), Miyazaki et al.
patent: 5477933 (1995-12-01), Nguyen
patent: 5578526 (1996-11-01), Akram et al.
patent: 5796417 (1998-08-01), Nobel
patent: 5944537 (1999-08-01), Smith et al.
patent: 6068669 (2000-05-01), Farnworth et al.
patent: 6245594 (2001-06-01), Wu et al.
patent: 6255740 (2001-07-01), Tsuji et al.
patent: 6265245 (2001-07-01), Farnworth et al.
patent: 6274821 (2001-08-01), Echigo et al.
patent: 6372620 (2002-04-01), Oosawa et al.
patent: 6451627 (2002-09-01), Coffman
patent: 6469908 (2002-10-01), Patel et al.
patent: 6524115 (2003-02-01), Gates et al.
patent: 6528349 (2003-03-01), Patel et al.
patent: 6528874 (2003-03-01), Lijima et al.
patent: 6548328 (2003-04-01), Sakamoto et al.
patent: 6582983 (2003-06-01), Runyon et al.
patent: 6589855 (2003-07-01), Miyamoto et al.
patent: 6589870 (2003-07-01), Katoh
patent: 6617236 (2003-09-01), Oosawa et al.
patent: 6646337 (2003-11-01), Lijima et al.
patent: 6671947 (2004-01-01), Bohr
patent: 6674297 (2004-01-01), Florence, Jr. et al.
patent: 6753614 (2004-06-01), Yamazaki et al.
patent: 6782610 (2004-08-01), Lijima et al.
patent: 6828221 (2004-12-01), Lijima et al.
patent: 6884709 (2005-04-01), Lijima et al.
patent: 6908792 (2005-06-01), Bruce et al.
patent: 7244125 (2007-07-01), Brown et al.
patent: 2002/0171133 (2002-11-01), Mok et al.
patent: 2003/0003779 (2003-01-01), Rathburn
patent: 2003/0092220 (2003-05-01), Akram
patent: 2003/0099097 (2003-05-01), Mok et al.
patent: 2003/0103338 (2003-06-01), Vandentop et al.
patent: 2003/0207492 (2003-11-01), Maeda et al.
patent: 2004/0043533 (2004-03-01), Chua et al.
patent: 2004/0089464 (2004-05-01), Yamada
patent: 2004/0099960 (2004-05-01), Adae-Amoakoh et al.
patent: 2004/0129451 (2004-07-01), Wachtler
patent: 2005/0003650 (2005-01-01), Ramanathan et al.
patent: 2005/0026476 (2005-02-01), Mok et al.
patent: 2005/0239275 (2005-10-01), Muthukumar et al.
patent: 2005/0263869 (2005-12-01), Tanaka et al.
patent: 2005/0282374 (2005-12-01), Hwang et al.
patent: 2006/0038303 (2006-02-01), Sterrett et al.
patent: 2006/0046433 (2006-03-01), Sterrett et al.
patent: 2006/0077644 (2006-04-01), Nickerson et al.
patent: 2006/0094340 (2006-05-01), Ouderkirk et al.
patent: 2006/0112550 (2006-06-01), Kim et al.
patent: 2007/0001277 (2007-01-01), Ichikawa
patent: 2007/0007983 (2007-01-01), Salmon
Masahiro Sunohara et al., “Development of Wafer Thinning and Double-Side Bumping Technologies for the Three-Dimensional Stacked LSI”, 2002 Electronic Components and Technology Conference, pp. 238-245.
Naotaka Tanaka et al., “Guidelines for Structural and Material-System Design of a Highly Reliable 3D die-Stacked Module with Copper Through-Vias”, 2003 Electronic Components and Technology Conference, pp. 597-602.
Naotaka Tanaka et al., “Mechanical Effects of Copper Through-Vias in a 3D Die-Stacked Module”, 2002 Electronic Components and Technology Conference, pp. 473-479.
Kazumasa Tanida et al., “Ultra-high-density 3D Chip Stacking Technology”, 2003 Electronic Components and Technology Conference, pp. 1084-1089.
Manabu Tomisaka et al., “Electroplating Cu Fillings for Through-Vias for Three-Dimensional Chip Stacking”, 2002 Electronic Components and Technology Conference, pp. 1432-1438.
Mitsuo Umemoto et al., “Non-metallurgical Bonding Technology with Super-narrow Gap for 3D Stacked LSI”, 2002 Electronics Packaging Technology Conference, pp. 285-288.
Mitsuo Umemoto et al., “Superfine Flip-Chip Interconnection in 20μm-Pitch Utilizing Reliable Microthin Underfill Technology for 3D Stacked LSI”, 2002 Electronic Components and Technology Conference, 2002 Electronic Components and Technology Conference, pp. 1454-1459.
Terry L. Sterrett et al., “Thinning Semiconductor Wafers”, U.S. Appl. No. 10/925,775, Filed Aug. 25, 2004.
Terry L. Sterrett et al., “Etched Interposer for Integrated Circuit Devices”, U.S. Appl. No. 10/924,396, Filed Aug. 23, 2004.
Sriram Muthukumar et al., “Compliant Multi-Composition Interconnects”, U.S. Appl. No. 10/832,178, Filed Apr. 26, 2004.
Mould et al., “A New Alternative for Temporary Wafer Mounting,” (2002) GaAsMANTECH Conference, 4 pages.
North Corporation, “Neo-Manhattan Technology: A Novel HDI Manufacturing Process,” from IPC Flex & Chips Symposium, Feb. 2003, 32 pages.
Mallik, D. et al., “Advanced Package Technologies for High-Performance Systems,” Intel Technology Journal, vol. 9, Issue 4, Nov. 9, 2005, pp. 259-272.
Dataweek, “Stacked-CSP Delivers Flexibility, Reliability and Space-Saving Capabilities,”, Aug. 27, 2003, 5 pages, retrieved from the internet at: http://dataweek.co.za
ews.asp?pklNewsID=11744&pklIssueID=348pklCategoryID=36.
Intel Corporation, “Silicon: Packaging Solutions for a Mobile Marketplace,” retrieved from the internet at: http://web.archive.org/web/20040101-20041231re—/http://www.intel.com/research/silicon/mobilepackaging.htm.
McCormick, A., “Pins & Vias: New Processes, Materials Extend Flexible Circuit Use,” May 2003, 3 pages, retrieved from the internet at: http:/
easia.nikkeibp.com
ea/200305/manu—244639.html.
Chipsupply.com, “Chip Scale Packaging (CSP),” 5 pages, retrieved from the internet at: http:// www.chipsupply.com/corporate/interconnect%20solutions/chip%20scale.htm, date is unknown.
IMEC, “Advanced Packaging Technologies to Bridge the Interconnect Technology Gap,” pp. 1-8, date is unknown.
Intel Corporation, “The Chip Scale Package (CSP)”, 2000 Packaging Databook, 2000, Ch 15, pp. 15-1 through 15-16.
IVF—The Swedish Institute of Production Engineering Research, “Chapter B: Flip-Chip Technology”, 7 pages, retrieved from the internet at: http://extra.ivf.se
gl/B-Flip-Chip/ChapterB1.htm, date is unknown.
Mahajan R. et al., “The Evolution of Microprocessor Packaging,” Intel Technology Journal, Q3, 2000, pp. 1-10.
Mahajan, R. et al., “Emerging Directions for Packaging Technologies,” Intel Technology Journal, vol. 6, Issue 2, May 2002, pp. 62-75.
U.S. Appl. No. 10/924,396, Office Action, mailed on Nov. 13, 2007, USPTO, 15 pages.
Sterrett et al., Amendment and Response to Office Action for U.S. Appl. No. 10/924,396, entitled: Etched Interposer for Integrated Circuit Devices, response filed Feb. 13, 2008, 11 pages.
U.S. Appl. No. 10/924,396, Office Action, mailed on Sep. 13, 2006, USPTO, 9 pages.
Sterrett et al., Amendment and Response to Office Action for U.S. Appl. No. 10/924,396, entitled: Etched Interposer for Integrated Circuit Devices, response filed Dec. 13, 2006, 9 pages.
U.S. Appl. No. 10/925,775, Office Action, mailed on Oct. 17, 2007, USPTO, 5 pages.
Sterrett et al., Appeal Brief for U.S. Appl. No. 10/925,775, entitled: Thinning Semiconductor Wafers, Appeal Brief filed Jan. 11, 2008, 13 pages.
U.S. Appl. No. 10/925,775, Office Action, mailed on Apr. 26, 2007, USPTO, 6 pages.
Sterrett et al., Amendment and Response to Office Action for U.S. Appl. No. 10/925,775, entitled: Thinning Semiconductor Wafers, response filed Jul. 23, 2007, 3 pages.
U.S. Appl. No. 10/925,775, Office Action, mailed on Nov. 28, 2006, USPTO, 6 pages.
Sterrett et al., Amendment and Response to Office Action for U.S. Appl. No. 10/925,775, entitled: Thinning Semiconductor Wafers, response filed Dec. 8, 2005, 3 pages.
U.S. Appl. No. 10/925,775, Office Action, mailed on Aug. 8, 2006, USPTO, 8 pages.
Sterrett et al., Amendment and Response to Office Action for U.S. Appl. No. 10/925,775, entitled: Thinning Semiconductor

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Thin silicon based substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Thin silicon based substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin silicon based substrate will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3999055

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.