Thin passivation layer on 3D devices

Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means

Reexamination Certificate

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Reexamination Certificate

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07354862

ABSTRACT:
Embodiments of the invention include a device with stacked substrates. Conducting interconnecting structures of one substrate are bonded to conducting interconnecting structures of another substrate. A passivating layer may be on the conducting interconnecting structures between the substrates and may be formed by an atomic layer deposition process or a with a Langmuir-Blodgett technique.

REFERENCES:
patent: 5627106 (1997-05-01), Hsu
patent: 6168873 (2001-01-01), Ikeda et al.
patent: 6432811 (2002-08-01), Wong
patent: 6596640 (2003-07-01), Fishcer et al.
patent: 2003/0186535 (2003-10-01), Wong et al.
patent: 2005/0025942 (2005-02-01), Fischer et al.

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