Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-10-30
2003-02-04
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S050000, C257S529000, C438S131000, C438S467000, C438S600000
Reexamination Certificate
active
06515344
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device formed on a semiconductor substrate. The invention has particular applicability in manufacturing semiconductor devices requiring one-time programmability.
BACKGROUND ART
Integrated circuit (IC) products require a capability of one time programmability. By serializing individual dies on a wafer for identification by a well-known one-time programming or “fuse programming” technique, and storing this data in an information data base, yield can be improved because the manufacturer can trace where a particular chip originated. For example, after the chip is in service, it can be traced to a lot, etc. Furthermore, after wafer processing is completed, wafers are subjected to a “wafer sort” where the dies are tested before being packaged. Generally, yield may be as low as 50%, and since packaging is costly, the manufacturer prefers to avoid packaging defective devices. Therefore, the dies are tested in wafer form. If information about the wafer is known because the dies were serialized with fuse programming, the manufacturer thereby knows that the dies are associated with a particular wafer and/or a particular position on the wafer (e.g., on the edge or in the middle of the wafer). This information facilitates the diagnosis of processing problems. For example, a yield map can be produced that will point out defect patterns which can then be traced to a particular process or piece of processing equipment.
One-time programmability has been done in prior art by three basic approaches:
1. An array of fuse links that may be “blown open.” An unblown fuse has a low resistance and a blown fuse has a high resistance, usually at the level of a functional open circuit.
2. An anti-fuse that may be “blown shorted.” An unblown anti-fuse has a high resistance, often functionally an open circuit. A blown anti-fuse has a low resistance, usually a resistance value less than 1000 ohms.
3. A programmable transistor with a floating gate. These are devices such as EPROMS, EEPROMS and flash memories.
The general trend in high-speed logic technologies has been towards a reduction in power supply voltages, with IC's currently being produced with 2.0 volts and less operating voltage. The maximum voltage capability of these transistors is often well under 10 volts. Disadvantageously, conventional fuse links require a potential of greater than 10 volts at currents greater than 10 amperes for reliable fuse blowing. Likewise, conventional amorphous polysilicon anti-fuses also require greater than 10 volts at currents greater than 100 &mgr;Å for reliable fuse blowing. Therefore, using basic logic transistors to blow fuses is impractical. Furthermore, although programmed fuse links require less current to blow, the required programming voltage is still too high to use basic logic transistors for anti-fuse blowing.
Thus, for both fuse or anti-fuse programming, fuse devices having a higher than standard voltage breakdown capability are required. Forming such non-standard devices adds cost and complexity to the integrated circuit process and wafer cost. Likewise, to embed programmable transistors, such as flash memory cells, into a logic device also adds cost and complexity to the integrated circuit, even more than simply adding high voltage transistors as fuses or anti-fuses. Unless the IC needs megabits of programmable sites, this approach is not cost effective. IC's commonly need only a modest amount of bits to be one-time programmable, anywhere from a few bits to several kilobits.
There exists a need for a one-time programming capability that does not unduly add to the cost of manufacturing the semiconductor device.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of providing one-time programming capability without added manufacturing costs.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by an anti-fuse of a semiconductor device, the anti-fuse comprising an active region in a semiconductor substrate; a channel region adjacent to the active region in the substrate; a gate oxide layer on a main surface of the substrate above the channel region; and a conductive gate on the gate oxide layer, the gate having about a minimum dimension according to the design rules of the semiconductor device; wherein the gate, channel region and active region are arranged such that the gate oxide fails when a programming voltage is applied between the gate and the active region.
Another aspect of the present invention is a method for providing one-time programmability for a semiconductor device formed on a semiconductor substrate, the method comprising providing an anti-fuse by forming an active region in the semiconductor substrate, a channel region adjacent to the active region in the substrate, a gate oxide layer on a main surface of the substrate above the channel region, and a conductive gate on the gate oxide layer; and applying a programming voltage between the gate and the active region to cause the gate oxide to fail.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
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patent: 4881114 (1989-11-01), Mohsen et al.
patent: 4943538 (1990-07-01), Mohsen et al.
patent: 5057451 (1991-10-01), McCollum
patent: 5110754 (1992-05-01), Lowrey et al.
patent: 5635873 (1997-06-01), Thrower et al.
patent: 5742555 (1998-04-01), Marr et al.
patent: 0495317 (1992-07-01), None
Advanced Micro Devices , Inc.
Kang Donghee
Loke Steven
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