Thin form factor flip chip ball grid array

Details Thin form factor flip chip ball grid array Thin form factor flip chip ball grid array

2000-08-30

2002-08-27

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S680000, C257S681000, C257S701000

Reexamination Certificate

active

06441499

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to package construction of integrated circuits. More specifically, but without limitation thereto, the present invention relates to the construction of an integrated circuit package for a flip chip plastic ball grid array (BGA).
FIG. 1
is a side view diagram of a flip chip ball grid array package
100
of the prior art. Shown are a stiffener
102
, a heat spreader
104
, a die
106
, a laminated substrate
108
, wafer bumps
110
, an underfill
112
, a thermally conductive adhesive
114
, solder balls
116
, a stiffener adhesive
118
, and a second level board
120
.
The stiffener
102
and the heat spreader
104
typically have the same area as the flip chip plastic ball grid array package
100
. The die
106
has a standard thickness of
725
microns and is electrically connected to the substrate
108
by the wafer bumps
110
, which are typically made of a eutectic solder. The spaces between the wafer bumps
110
and the die
106
are underfilled with the underfill
112
.
The stiffener
102
is typically attached to the substrate
108
and the heatspreader
104
by the stiffener adhesive
118
to protect the ball grid array package
100
from flexure damage. The heatspreader
104
is attached to the stiffener
102
to conduct heat away from the die
106
through the thermally conductive adhesive
114
. The flip chip ball grid array package
100
may be mounted on a second level package
120
by the solder balls
116
.
Disadvantageously, the composite coefficient of thermal expansion (CTE) of the ball grid array package
100
is lower than the coefficient of thermal expansion of the second level board
120
because the die
106
has a coefficient of thermal expansion that is several times lower than that of the second level board
120
. The difference in the coefficients of thermal expansion causes cracking of the solder balls
116
connecting the substrate
108
to the second level board
120
and results in poor second level package reliability. A ball grid array package is needed that can withstand manufacturing temperature cycles without damage to the solder ball interconnects.
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a method and apparatus for a thermally tolerant flip chip ball grid array package.
In one embodiment, the invention may be characterized as a method for making a flip chip ball grid array package that includes the step of thinning a die for matching a composite coefficient of thermal expansion to that of a second level board.
In another embodiment, the invention may be characterized as an apparatus for a flip chip ball grid array package that includes a thin die having a die thickness for matching a composite coefficient of thermal expansion to that of a second level board.
The features and advantages summarized above in addition to other aspects of the present invention will become more apparent from the description, presented in conjunction with the following drawings.


REFERENCES:
patent: 5308980 (1994-05-01), Barton
patent: 5610442 (1997-03-01), Schneider
patent: 5956576 (1999-09-01), Toy
patent: 6163462 (2000-12-01), Buck
patent: 6204090 (2001-03-01), Boyle et al.
patent: 6279815 (2001-08-01), Correia
patent: 6281452 (2001-08-01), Prasad
patent: 6291884 (2001-09-01), Glenn
patent: 6303977 (2001-10-01), Schroen
patent: 405121587 (1993-05-01), None

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