Stock material or miscellaneous articles – Structurally defined web or sheet – Discontinuous or differential coating – impregnation or bond
Reexamination Certificate
2000-10-31
2002-10-15
Lam, Cathy (Department: 1775)
Stock material or miscellaneous articles
Structurally defined web or sheet
Discontinuous or differential coating, impregnation or bond
C428S209000, C174S257000, C174S261000, C174S264000
Reexamination Certificate
active
06465085
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a thin film wiring board with a via used for interlayer connection. More particularly, this invention relates to the thin film wiring board that allows manufacturing yield to be improved and a method for manufacturing the thin film wiring board. Further, this invention relates to a method for correcting a void defect occurring on the surface of a base substrate used for the thin film wiring board.
BACKGROUND OF THE INVENTION
In recent years, a multilayer thin film wiring board that enables high density wiring on an MCM (Multi Chip Module) board or the like has been in the actual use, and applied in electronic equipment such as a computer. This multilayer thin film wiring board is provided by laminating an insulating layer and a wiring layer. The insulating layer is generally made of polyimide and formed to be extremely thin by spin-coating. A high-density pattern is also formed on the wiring layer by using sputtering and a highly sensitive resist.
This multilayer thin film wiring board has a structure that allows the wiring and the power supply between electronic components by connecting LSI (Large Scale Integrated Circuit) packed on the surface of the board and terminals (signal terminal, power terminal, and ground terminal) of the electronic components such as input/output pins to a desired layer through vias.
In recent years, the multilayer thin film wiring board is also becoming denser in association with tighter packing of LSIs. Accordingly, at present, surface defects may easily be generated in the manufacturing process of the multilayer thin film wiring board, and reduction in the yield becomes an issue that should be taken care of. An effective solution to this problem is eagerly expected.
FIG.
10
and
FIG. 11
show general views of the MCM. As shown in
FIG. 10
, a plurality of LSI chips
69
are mounted on the thin film wiring board
68
, and cooling fins
71
for cooling are mounted above the chips. The input/output pins
70
for connection with a mother board not shown are provided in the opposite side to the cooling fins
70
with the LSI chip
69
in between.
The thin film wiring board
68
is structured with a thin film layer
74
formed on a ceramic substrate
72
as shown in
FIG. 11
, and a connection between the thin film wiring board
68
and the LSI chip not shown is made by a soldering bump
75
. The diameter of a via
73
provided in the ceramic substrate
72
is around 0.1 mm to 0.2 mm.
FIG. 12A
to
FIG. 12E
show cross-sectional views of the structure and the manufacturing process of a conventional multilayer thin film wiring board.
FIG. 12A
shows a ceramic substrate
1
having vias
2
a
and
2
b.
This ceramic substrate
1
is obtained by sintering a laminated thin-film ceramic sheet, and the surface
1
c
of this ceramic substrate
1
is flattened. A surface defect
3
a
occurs due to the difference between the hardness of the ceramic substrate
1
and that of the via
2
b.
Further, the surface
1
c
of the ceramic substrate
1
is supposed to have irregularities due to a phenomenon that ceramic particles are detached or a phenomenon that voids occurring at the time of sintering the ceramic substrate
1
are exposed.
In the manufacturing process using the ceramic substrate
1
shown in
FIG. 12A
, a via connecting pad
4
a
and a via connecting pad
4
b
are formed on the surface
1
c
of the ceramic substrate
1
as shown in
FIG. 12B
by means of sputtering or the like. During this process, a protrusion
4
c
is formed on the via connecting pad
4
a
caused by dust or the like, and a defect
3
b
occurs in the via connecting pad
4
b
under the influence of the surface defect
3
a
(see FIG.
12
A). In this state, a via
5
a
and a via
5
b
are formed so as to protrude upward on the respective surfaces of the via connecting pad
4
a
and the via connecting pad
4
b,
as shown in FIG.
12
C.
In the next manufacturing process, a polyimide insulating layer
6
(see
FIG. 12D
) as an insulator is formed on the surface
1
c
of the ceramic substrate
1
, and then the surface of the polyimide insulating layer
6
is polished as shown in FIG.
12
D. At this time, the top section of the protrusion
4
c
is shaved and thus exposed, while a tapered defect
3
d
is formed due to a defect
3
c
(see FIG.
12
C). Thus, the defective portion grows as follows: surface defect
3
a
→defect
3
b
→defect
3
c
→defect
3
d
as the manufacturing process proceeds along the steps of
FIG. 12A
to FIG.
12
D.
In the next manufacturing process, patterns
7
a
to
7
d
are formed on the surface of the polyimide insulating layer
6
shown in FIG.
12
E through the plating process, respectively. The pattern
7
a
and the via connecting pad
4
a
are short-circuited through the protrusion
4
c,
and in the same manner as explained above, the pattern
7
c
and the via connecting pad
4
b
are short-circuited through the protrusion
7
e
formed inside the defect
3
d
(see FIG.
12
D). In the normal state, the pattern
7
a
has to be insulated from the via connecting pad
4
a
and the pattern
7
c
has to be insulated from the via connecting pad
4
b
as well. That is, the multilayer thin film wiring board shown in
FIG. 12E
is regarded as a defective.
By the way, the conventional multilayer thin film wiring board is manufactured through the manufacturing process steps as shown in
FIG. 12B
to
FIG. 12E
as explained above. However, during this process, a large number of defects may be generated because of the irregularities on the surface such as the surface defect
3
a
and the protrusion
4
c.
Accordingly, the manufacturing yield is reduced. This reduction of the yield may result in increase in cost of the multilayer thin film wiring board.
That is, the pattern
7
a
and the pattern
7
b
shown in
FIG. 12E
should originally be insulated from each other, but are short-circuited through the protrusion
4
c,
the via connecting pad
4
a,
and the via
5
a.
In the same manner as the above case, the pattern
7
c
and the pattern
7
d
should originally be insulated from each other, but are short-circuited through the protrusion
7
e,
the via connecting pad
4
b,
and the via
5
b.
Recently, as the number of LSI terminals is increasing due to its higher density, the number of lines of wiring on the board that connects between LSIs is increasing, thus finer pitches of the wiring are demanded. This demand is stronger particularly for the thin film wiring board used in an MCM board, therefore, finer pitches of the wiring are progressing. The conventional method for manufacturing the thin film wiring board is shown in
FIG. 13A
to FIG.
13
G.
At step
1
, the ceramic substrate is sliced (around 0.1 mm to 0.3 mm), and holes are punched in the substrate (FIG.
13
A). Each of the holes is then filled with tungsten (W)
81
to form a thin green sheet
80
as shown in the figure. aluminum ceramic, ceramic of aluminum nitride, or glass ceramic are used as a material of the ceramic substrate, and tungsten
81
or molybdenum or the like is used as metal for conduction to be filled in the holes. When the material of the ceramic substrate is glass ceramic, copper (Cu) is also usable as metal for conduction to be filled in the holes.
At step
2
, a plurality of the green sheets
80
are laminated, pressurized, and sintered to form a sheet of base substrate
72
(see FIG.
13
B and FIG.
13
D). At this time, the tungsten
81
filled in the holes at step
1
becomes a via
73
which allows interlayer electric conduction.
At step
3
, the surface of the base substrate
72
is mechanically polished to flatten the irregularities of the surface (see FIG.
13
C and FIG.
13
E).
At step
4
, a chrome (Cr) layer or a titanium (Ti) layer as contact metal and a copper layer as a current-carrying layer at the time of plating are formed by a sputtering method. (Hereafter these layers are referred to as conductor layer as under plating. See FIG.
13
F).
At step
5
, a layer of copper
86
is formed in desired thickness on
Kikuchi Shunichi
Moriizumi Kiyokazu
Ozaki Norikazu
Sasahara Takami
Song Zhiyi
LandOfFree
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